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* Merge upstream to r134237 at Fri. 1st July 2011.Nowar Gu2011-07-01232-2508/+4301
|\ | | | | | | | | Conflicts: lib/Target/ARM/ARMCodeEmitter.cpp
| * Improve Mips back-end's handling of DBG_VALUE. Akira Hatanaka2011-07-015-23/+70
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher2011-07-011-0/+9
| | | | | | | | | | | | | | | | | | supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the ARM 't' register constraint. And another testcaseEric Christopher2011-07-011-0/+5
| | | | | | | | | | | | | | | | | | for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
| * We'll return a null RC by default if we can't match.Eric Christopher2011-07-011-2/+1
| | | | | | | | | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'x' constraint.Eric Christopher2011-07-011-0/+9
| | | | | | | | | | | | | | Part of rdar://9307836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
| * Capitalize the unsigned part of the initializer.Eric Christopher2011-06-301-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename Pair to RCPair lacking any better naming ideas.Eric Christopher2011-06-301-10/+10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use the correct registers on X86_64.Bill Wendling2011-06-301-4/+4
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134208 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix a problem with fast-isel return values introduced in r134018.Jakob Stoklund Olesen2011-06-301-2/+3
| | | | | | | | | | | | | | | | | | We would put the return value from long double functions in the wrong register. This fixes gcc.c-torture/execute/conversion.c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134205 91177308-0d34-0410-b5e6-96231b3b80d8
| * Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-309-86/+26
| | | | | | | | | | | | | | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'h' constraint.Eric Christopher2011-06-302-1/+10
| | | | | | | | | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-302-0/+19
| | | | | | | | | | | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.Eric Christopher2011-06-301-7/+8
| | | | | | | | | | | | | | | | | | No functional change. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8
| * Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-308-51/+60
| | | | | | | | | | | | | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
| * Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.cJakob Stoklund Olesen2011-06-301-3/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134193 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-303-24/+7
| | | | | | | | | | | | | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-302-19/+12
| | | | | | | | | | | | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-302-9/+10
| | | | | | | | | | | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134172 91177308-0d34-0410-b5e6-96231b3b80d8
| * Kill dead code.Jim Grosbach2011-06-301-1/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134131 91177308-0d34-0410-b5e6-96231b3b80d8
| * Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| | | | | | | | | | | | | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134130 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix ARMSubtarget feature parsing.Evan Cheng2011-06-301-10/+7
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134129 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-3056-145/+210
| | | | | | | | | | | | | | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
| * Recognize the xstorerng alias for VIA PadLock's xstore instruction.Joerg Sonnenberger2011-06-301-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8
| * Make sure we use the correct register class here since we'll need toEric Christopher2011-06-301-1/+2
| | | | | | | | | | | | | | care about spill values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134122 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix a small thinko for constant i64 lock/orq optimization where weEric Christopher2011-06-301-2/+4
| | | | | | | | | | | | | | | | | | we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134121 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-296-113/+55
| | | | | | | | | | | | | | | | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
| * Always adjust the stack pointer immediately after the call.Jakob Stoklund Olesen2011-06-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some x86-32 calls pop values off the stack, and we need to readjust the stack pointer after the call. This happens when ADJCALLSTACKUP is eliminated. It could happen that spill code was inserted between the CALL and ADJCALLSTACKUP instructions, and we would compute wrong stack pointer offsets for those frame index references. Fix this by inserting the stack pointer adjustment immediately after the call instead of where the ADJCALLSTACKUP instruction was erased. I don't have a test case since we don't currently insert code in that position. We will soon, though. I am testing a regalloc patch that didn't work on Linux because of this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134113 91177308-0d34-0410-b5e6-96231b3b80d8
| * In the ARM global merging pass, allow extraneous alignment specifiers. This passCameron Zwarich2011-06-291-2/+4
| | | | | | | | | | | | | | | | already makes the assumption, which is correct on ARM, that a type's alignment is less than its alloc size. This improves codegen with Clang (which inserts a lot of extraneous alignment specifiers) and fixes <rdar://problem/9695089>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134106 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove getRegClassForInlineAsmConstraint from the ARM port.Eric Christopher2011-06-292-59/+15
| | | | | | | | | | | | | | Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134095 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove todo.Eric Christopher2011-06-291-2/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134094 91177308-0d34-0410-b5e6-96231b3b80d8
| * Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-295-36/+8
| | | | | | | | | | | | | | | | | | The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a TODO for the Alpha port inline asm constraints.Eric Christopher2011-06-291-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134089 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move Alpha from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-32/+14
| | | | | | | | | | | | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134088 91177308-0d34-0410-b5e6-96231b3b80d8
| * Update comment for getRegForInlineAsmConstraint for Mips.Eric Christopher2011-06-291-3/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134087 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move the Blackfin port away from getRegClassForInlineAsmConstraint byEric Christopher2011-06-293-29/+22
| | | | | | | | | | | | | | | | | | creating a few specific register classes. Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134086 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove getRegClassForInlineAsmConstraint from MBlaze. Add a TODO commentEric Christopher2011-06-292-33/+7
| | | | | | | | | | | | | | | | | | for the port. Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134085 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove getRegClassForInlineAsmConstraint for Mips.Eric Christopher2011-06-292-48/+3
| | | | | | | | | | | | | | Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134084 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove getRegClassForInlineAsmConstraint from sparc.Eric Christopher2011-06-292-24/+0
| | | | | | | | | | | | | | Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134083 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move XCore from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-17/+14
| | | | | | | | | | | | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134080 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use getRegForInlineAsmConstraint instead of custom defining regclassesEric Christopher2011-06-292-56/+24
| | | | | | | | | | | | | | | | | | via vectors. Part of rdar://9643582 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134079 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix CMake build.NAKAMURA Takumi2011-06-291-1/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134055 91177308-0d34-0410-b5e6-96231b3b80d8
| * Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-298-398/+8
| | | | | | | | | | | | MCInstrItineraries) into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-2828-59/+58
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
| * Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-2813-25/+13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add MCInstrInfo registeration machinery.Evan Cheng2011-06-281-0/+6
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134026 91177308-0d34-0410-b5e6-96231b3b80d8
| * Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-2862-87/+112
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
| * - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-2838-470/+469
| | | | | | | | | | | | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
| * Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-286-227/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134018 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove warning: 'c0' may be used uninitialized in this function.Chad Rosier2011-06-281-1/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134014 91177308-0d34-0410-b5e6-96231b3b80d8
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