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* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0715-42/+48
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-076-28/+22
* ARM sched model: Use the right resources for DIVArnold Schwaighofer2013-06-071-1/+1
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-071-0/+16
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-071-0/+364
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-073-17/+19
* R600: Rewrite an awkward loop in R600MachineSchedulerVincent Lejeune2013-06-061-7/+15
* Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"Arnold Schwaighofer2013-06-061-364/+0
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+364
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-063-0/+125
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+209
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-061-0/+155
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-061-4/+45
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-061-18/+21
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-061-11/+15
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-061-27/+35
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-061-3/+6
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-061-2/+4
* ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer2013-06-061-46/+61
* ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer2013-06-061-52/+86
* R600: Remove leftover code in R600MachineScheduler.cppVincent Lejeune2013-06-061-16/+0
* Cast to the correct type. Pointer, not reference.Bill Wendling2013-06-061-1/+1
* R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized]NAKAMURA Takumi2013-06-061-1/+1
* R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable]NAKAMURA Takumi2013-06-061-0/+1
* Trailing linefeed.NAKAMURA Takumi2013-06-061-1/+0
* Cast to the proper type.Bill Wendling2013-06-061-1/+1
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-0612-39/+39
* R600: Replace predicate loop with predicate functionTom Stellard2013-06-051-11/+13
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-054-0/+370
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-052-1/+32
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+4
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-052-1/+5
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-051-37/+49
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-054-7/+89
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-051-0/+2
* This is a simple patch that changes RRX and RRXS to accept all registers as o...Mihai Popa2013-06-051-1/+1
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-053-4/+40
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-054-370/+0
* Handle relocations that don't point to symbols.Rafael Espindola2013-06-052-11/+10
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-044-0/+370
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-045-47/+186
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-041-1/+2
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-048-1277/+207
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-041-0/+16
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+364
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-041-0/+120
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+209
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-041-0/+155
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-041-4/+45
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-041-18/+21
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