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* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-1626-618/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid isMoveInstr when printing XCore pseudo-moves.Jakob Stoklund Olesen2010-07-161-7/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108566 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MI.isCopy.Jakob Stoklund Olesen2010-07-161-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108565 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a small local function for a single remaining late isMoveInstr call inJakob Stoklund Olesen2010-07-161-24/+42
| | | | | | Thumb2ITBlockPass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108564 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-1612-21/+21
| | | | | | | thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep valgrind quiet.Jakob Stoklund Olesen2010-07-161-1/+6
| | | | | | | The isLive() method can read uninitialized memory, but it still gives correct results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108561 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit COPY instead of FMR/FMSD instructions for floating point conversion onJakob Stoklund Olesen2010-07-162-12/+9
| | | | | | PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108555 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing attributes to cpp backend.Eli Friedman2010-07-161-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108547 91177308-0d34-0410-b5e6-96231b3b80d8
* Accept registers with P modifier. PR 5314.Dale Johannesen2010-07-161-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108545 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memoryJakob Stoklund Olesen2010-07-161-0/+19
| | | | | | | | | operands. Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't since missing memoperands should not affect correctness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108540 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKillJakob Stoklund Olesen2010-07-167-182/+1
| | | | | | | | | pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108536 91177308-0d34-0410-b5e6-96231b3b80d8
* Search for a free FP register instead of just assuming FP7 is not in use.Jakob Stoklund Olesen2010-07-161-6/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108535 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow x87 FP registers to be alive globally in a function.Jakob Stoklund Olesen2010-07-162-37/+389
| | | | | | | | | | | | | | | | FP_REG_KILL instructions are still inserted, but can be disabled by passing -live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly. CFG edges are partioned into bundles where the x87 stack must be allocated identically. Code is insertad at the end of each basic block that shuffles the live FP registers to match the outgoing bundles expectations. This fix is in preparation for some upcoming register allocator improvements that may extend the live range of registers beyond a basic block, similar to LICM. It also provides a nice runtime speedup if you are building with -mfpmath=387. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108529 91177308-0d34-0410-b5e6-96231b3b80d8
* Split -enable-finite-only-fp-math to two options:Evan Cheng2010-07-154-24/+20
| | | | | | | -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
* fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3,Chris Lattner2010-07-151-1/+1
| | | | | | | | | this fixes rdar://8192860. Unfortunately it can only be triggered with llc because llvm-mc matches another (correctly encoded) version of this, so no testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108454 91177308-0d34-0410-b5e6-96231b3b80d8
* Random note about bswap.Eli Friedman2010-07-151-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108396 91177308-0d34-0410-b5e6-96231b3b80d8
* Last COPY conversion.Jakob Stoklund Olesen2010-07-141-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108387 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove restriction on NEON alignment values. Some of the NEON ld/stBob Wilson2010-07-143-9/+4
| | | | | | | | instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108386 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TargetOpcode::COPY instead of X86-native register copy instructions whenJakob Stoklund Olesen2010-07-142-30/+27
| | | | | | | lowering atomics. This will allow those copies to still be coalesced after TII::isMoveInstr is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108385 91177308-0d34-0410-b5e6-96231b3b80d8
* fix indentationChris Lattner2010-07-141-9/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108368 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't pass StringRef by reference.Benjamin Kramer2010-07-1424-41/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h,Chris Lattner2010-07-142-100/+8
| | | | | | | | patch by Michael Spencer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108342 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve 64-subtraction of immediates when parts of the immediate can fitJim Grosbach2010-07-142-11/+40
| | | | | | | | | | | | | in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing address register update to t2LDM_RET instruction.Bob Wilson2010-07-141-1/+1
| | | | | | | Patch by Brian Lucas. PR7636. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
* A couple potential optimizations inspired by comment 4 in PR6773.Eli Friedman2010-07-141-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108328 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR7193 was overly conservative. The only case where sibcall calleeEvan Cheng2010-07-141-6/+12
| | | | | | | | | | | address cannot be allocated a register is in 32-bit mode where the first three arguments are marked inreg. In that case EAX, EDX, and ECX will be used for argument passing. This fixes PR7610. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108327 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for NEON VMVN immediate instructions.Bob Wilson2010-07-143-7/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
* The bits in the cmode field of 32-bit VMOV immediate instructions all dependBob Wilson2010-07-141-2/+2
| | | | | | | of the value of the immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108323 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a bug found by a warning I added to clang this morning.Chris Lattner2010-07-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108309 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.Bob Wilson2010-07-141-0/+29
| | | | | | | Radar 7373643. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't propagate debug locations to instructions for materializingDan Gohman2010-07-141-1/+1
| | | | | | | | constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108302 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit compare instructions and a bunch of testcasesBruno Cardoso Lopes2010-07-131-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-133-192/+78
| | | | | | | NEON VMOV-immediate instructions. This simplifies some things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX 256-bit conversion instructionsBruno Cardoso Lopes2010-07-134-15/+105
| | | | | | | Add the x86 VEX_L form to handle special cases where VEX_L must be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a check that pusha cannot be encoded in 64-bit mode.Kevin Enderby2010-07-131-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108265 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend the r107852 optimization which turns some fp compare to code sequence ↵Evan Cheng2010-07-133-71/+240
| | | | | | using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).Evan Cheng2010-07-132-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
* -enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.Evan Cheng2010-07-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108254 91177308-0d34-0410-b5e6-96231b3b80d8
* rotate CallInst operandsGabor Greif2010-07-131-5/+5
| | | | | | | | | | | | | | | | | | | with this commit the callee moves to the end of the operand array (from the start) and the call arguments now start at index 0 (formerly 1) this ordering is now consistent with InvokeInst this commit only flips the switch, functionally it is equivalent to r101465 I intend to commit several cleanups after a few days of soak period git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108240 91177308-0d34-0410-b5e6-96231b3b80d8
* Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson2010-07-134-77/+84
| | | | | | | avoid replicated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
* my work on adding segment registers to LEA missed the Chris Lattner2010-07-131-12/+3
| | | | | | | | disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit packed logical formsBruno Cardoso Lopes2010-07-131-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit unop arithmetic instructionsBruno Cardoso Lopes2010-07-131-53/+86
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
* Since AVX is a superset of all SSE versions, only use HasAVX for AVX ↵Bruno Cardoso Lopes2010-07-132-81/+77
| | | | | | instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108222 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some SIMD fragment code into X86InstrFragmentsSIMD so that theDavid Greene2010-07-122-336/+336
| | | | | | | | utility classes can be used from multiple files. This will aid transitioning to a new refactored x86 SIMD specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108213 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256 binary arithmetic instructionsBruno Cardoso Lopes2010-07-121-7/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
* More refactoring of basic SSE arith instructions. Open room for 256-bit ↵Bruno Cardoso Lopes2010-07-121-207/+158
| | | | | | instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108204 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply the SSE dependence idiom for SSE unary operations toDan Gohman2010-07-121-2/+8
| | | | | | | | SD instructions too, in addition to SS instructions. And add a comment about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108191 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some code that doesn't appear to do anything. All the ARM callBob Wilson2010-07-121-5/+0
| | | | | | | | | instructions already have implicit defs of LR. The comment suggests that this is intended to fix something like pr6111, but it doesn't really do that either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108186 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit MOVMSK formsBruno Cardoso Lopes2010-07-121-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
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