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* Add a new MOV8rr_NOREX, and make X86's copyRegToReg use it whenDan Gohman2009-04-152-5/+20
| | | | | | | | | either the source or destination is a physical h register. This fixes sqlite3 with the post-RA scheduler enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69111 91177308-0d34-0410-b5e6-96231b3b80d8
* GR8_NOREX can contain the H registers, since they don't requireDan Gohman2009-04-151-2/+3
| | | | | | | REX prefixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69108 91177308-0d34-0410-b5e6-96231b3b80d8
* For the h-register addressing-mode trick, use the correct value forDan Gohman2009-04-141-1/+14
| | | | | | | any non-address uses of the address value. This fixes 186.crafty. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69094 91177308-0d34-0410-b5e6-96231b3b80d8
* Some of GR8_NOREX registers are only available in 64-bit mode.Evan Cheng2009-04-141-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle aggregate type arguments to direct and indirect calls.Sanjiv Gupta2009-04-144-35/+101
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69022 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-132-16/+16
| | | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply 68847.Devang Patel2009-04-132-0/+4
| | | | | | | | Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68964 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement x86 h-register extract support.Dan Gohman2009-04-137-98/+359
| | | | | | | | | | | | | | | | | | | | | | | | | - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove x86's special-case handling for ISD::TRUNCATE andDan Gohman2009-04-131-85/+0
| | | | | | | | | ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle these cases, and the scheduling issues observed earlier appear to be resolved now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68959 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix copy+pastos in comments.Dan Gohman2009-04-131-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68958 91177308-0d34-0410-b5e6-96231b3b80d8
* List the l registers before h registers, for consistency.Dan Gohman2009-04-131-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68954 91177308-0d34-0410-b5e6-96231b3b80d8
* Use X86::SUBREG_8BIT instead of hard-coding the equivalent constant.Dan Gohman2009-04-131-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68951 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment about MOVSX64rr8.Dan Gohman2009-04-131-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68950 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another hard-coded constant to use X86AddrNumOperands.Dan Gohman2009-04-131-1/+1
| | | | | | | This unbreaks the JIT on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68948 91177308-0d34-0410-b5e6-96231b3b80d8
* X86-64 TLS support for local exec and initial exec.Rafael Espindola2009-04-133-10/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68947 91177308-0d34-0410-b5e6-96231b3b80d8
* While passing arg of types larger than char only one byte at lower end was ↵Sanjiv Gupta2009-04-131-1/+1
| | | | | | getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68946 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new "available_externally" linkage type. This is intendedChris Lattner2009-04-131-0/+2
| | | | | | | | | to support C99 inline, GNU extern inline, etc. Related bugzilla's include PR3517, PR3100, & PR2933. Nothing uses this yet, but it appears to work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68940 91177308-0d34-0410-b5e6-96231b3b80d8
* In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matchingRafael Espindola2009-04-121-3/+8
| | | | | | | | only if symbolic addresses are RIP relatives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68924 91177308-0d34-0410-b5e6-96231b3b80d8
* refactor some code into X86DAGToDAGISel::MatchWrapperRafael Espindola2009-04-121-44/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68915 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a cross-block fastisel crash handling overflow intrinsics.Chris Lattner2009-04-121-5/+16
| | | | | | | See comment for details. This fixes rdar://6772169 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68890 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify code by using IntrinsicInst.Chris Lattner2009-04-121-69/+54
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68887 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new TargetInstrDesc::hasImplicitUseOfPhysReg andChris Lattner2009-04-121-15/+3
| | | | | | | | hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r68847. It breaks the build on non-Darwin targets, with this messageDan Gohman2009-04-112-2/+0
| | | | | | | | | from the assembler: Error: unknown pseudo-op: `.debug_inlined' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68863 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep track of inlined functions and their locations. This information is ↵Devang Patel2009-04-112-0/+2
| | | | | | | | | | collected when nested llvm.dbg.func.start intrinsics are seen. (Right now, inliner removes nested llvm.dbg.func.start intrinisics during inlining.) Create debug_inlined dwarf section using these information. This info is used by gdb, at least on Darwin, to enable better experience debugging inlined functions. See DwarfWriter.cpp for more information on structure of debug_inlined section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68847 91177308-0d34-0410-b5e6-96231b3b80d8
* Added code to handle spilling and reloading of FSRs.Sanjiv Gupta2009-04-104-14/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68783 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't fold a load if the other operand is a TLS address.Rafael Espindola2009-04-101-6/+27
| | | | | | | | | | | | | | | | With this we generate movl %gs:0, %eax leal i@NTPOFF(%eax), %eax instead of movl $i@NTPOFF, %eax addl %gs:0, %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68778 91177308-0d34-0410-b5e6-96231b3b80d8
* a few fixes to "addrspace(256) is reference offset of GS segment register".Chris Lattner2009-04-101-17/+60
| | | | | | | It turns out that there are still several problems with this, will file a bugzilla. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68749 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass in the std::string parameter instead of returning it by value.Bill Wendling2009-04-101-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68747 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the obsolete SelectionDAG::getNodeValueTypes and simplifyDan Gohman2009-04-092-10/+9
| | | | | | | code that uses it by using SelectionDAG::getVTList instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68744 91177308-0d34-0410-b5e6-96231b3b80d8
* Give register alias checking the hash table treatment too.Owen Anderson2009-04-091-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr3954. The register scavenger asserts for inline assembly withBob Wilson2009-04-091-13/+0
| | | | | | | | | | | | | register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
* The way we are trying to figure out banksel immediate operand may yield ↵Sanjiv Gupta2009-04-091-2/+3
| | | | | | different results for different type of insns. This will eventually need to be changed but currently let us prevent the crash in cases of incorrect detection of banksel operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68713 91177308-0d34-0410-b5e6-96231b3b80d8
* Arguments to indirect calls were being passed incorrectly. They are not ↵Sanjiv Gupta2009-04-091-2/+6
| | | | | | fixed to start after return value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68705 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix code size computation on x86-64, patch by Zoltan Varga!Chris Lattner2009-04-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68690 91177308-0d34-0410-b5e6-96231b3b80d8
* r68576 unconverd a bug in PIC16 port (Thanks to Dan Gohman) where we were ↵Sanjiv Gupta2009-04-091-5/+10
| | | | | | custom lowering an ADD to ADDC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68671 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert TargetRegisterInfo's super-register checking to use a pre-computed ↵Owen Anderson2009-04-091-3/+5
| | | | | | hash table just like subregister checking does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix grammaros in comments.Dan Gohman2009-04-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68666 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 68552.Rafael Espindola2009-04-0817-194/+234
| | | | | | | | Tested by bootstrapping llvm-gcc and using that to build llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3795: Apply Dan's suggested fix forBob Wilson2009-04-081-2/+6
| | | | | | | ARMTargetLowering::isLegalAddressingMode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68619 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid a hard coded constant.Rafael Espindola2009-04-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68603 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit .line debug directives for stoppoints. The debug location is retrieved ↵Sanjiv Gupta2009-04-085-24/+19
| | | | | | by the MachineInstr itself, rather than by custom handling the DBG_STOPPOINT nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68602 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle indirect function calls.Sanjiv Gupta2009-04-085-89/+346
| | | | | | | | | Every function has the address of its frame in the beginning of code section. The frame address is retrieved and used to pass arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68597 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for using modeling implicit-zero-extension on x86-64Dan Gohman2009-04-083-9/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling2009-04-0717-231/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce code duplication on the TLS implementation.Rafael Espindola2009-04-0717-193/+231
| | | | | | | | | | | | This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
* PR2985 / <rdar://problem/6584986>Jim Grosbach2009-04-077-194/+318
| | | | | | | | | | | | When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle 'a' modifier in ARM inline assembly.Bob Wilson2009-04-061-0/+3
| | | | | | | Patch by Richard Pennington. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68464 91177308-0d34-0410-b5e6-96231b3b80d8
* Map stack based frameindices for spills to zero based indices that can be ↵Sanjiv Gupta2009-04-065-33/+62
| | | | | | accessed based on an external symbol defining the location of temporary data for a function. For example: we have spill slots addressed as foo.tmp + 0, foo.tmp + 1 etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68442 91177308-0d34-0410-b5e6-96231b3b80d8
* Wrap some lines to fix indentation problems.Bob Wilson2009-04-031-30/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68405 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some comments.Bob Wilson2009-04-031-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68404 91177308-0d34-0410-b5e6-96231b3b80d8
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