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* Indexed loads each has 2 outputs.Evan Cheng2007-08-011-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40658 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-315-1117/+1117
| | | | | | | | | | mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8
* Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc ↵Evan Cheng2007-07-316-235/+248
| | | | | | (v4f32 s2v (f32 load ))), 0) -> (i32 load ) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40628 91177308-0d34-0410-b5e6-96231b3b80d8
* This isn't safe when there are uses of load's chain result.Evan Cheng2007-07-311-11/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40617 91177308-0d34-0410-b5e6-96231b3b80d8
* Use tabs more consistently in assembler pseudo-ops.Dan Gohman2007-07-302-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40594 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the comment for getClosestTargetForJIT to reflect the fact thatDan Gohman2007-07-301-4/+3
| | | | | | | it does not have a Module parameter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40590 91177308-0d34-0410-b5e6-96231b3b80d8
* More explicit keywords.Dan Gohman2007-07-301-1/+1
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* Vector fneg must be expanded into fsub -0.0, X.Evan Cheng2007-07-303-2/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the x86 backend to use extract_subreg for truncation operations. ↵Christopher Lamb2007-07-296-113/+37
| | | | | | Passes DejaGnu, SingleSource and MultiSource. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40578 91177308-0d34-0410-b5e6-96231b3b80d8
* Add register info needed to use subreg sets on X86.Christopher Lamb2007-07-281-2/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40572 91177308-0d34-0410-b5e6-96231b3b80d8
* Trampoline codegen support for X86-32.Duncan Sands2007-07-275-12/+130
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40566 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 40504, but with a fix for the segfault it caused in oggenc:Dan Gohman2007-07-273-75/+42
| | | | | | | | | | Make the alignedload and alignedstore patterns always require 16-byte alignment. This way when they are used in the "Fs" instructions, in which a vector instruction is used for a scalar purpose, they can still require the full vector alignment. And add a regression test for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40555 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for trampolines, except for X86 codegen which isDuncan Sands2007-07-278-3/+34
| | | | | | | still under discussion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 40504 for now. It's breaking oggenc.Evan Cheng2007-07-273-35/+70
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40547 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure epilogue esp adjustment is placed before any terminator and pop ↵Evan Cheng2007-07-261-2/+3
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40538 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't pollute the meaning of isUnpredicatedTerminator.Evan Cheng2007-07-261-7/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40537 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor bug.Evan Cheng2007-07-261-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40535 91177308-0d34-0410-b5e6-96231b3b80d8
* In the .loc directive, print the fields as "debug" fields, so theyDan Gohman2007-07-261-1/+1
| | | | | | | don't get decorated as if for immediate fields for instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40529 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a whitespace difference between CMPSSrr and CMPSDrr.Dan Gohman2007-07-261-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40528 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-0/+12
| | | | | | MBB's. PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
* Same goes for constantpool, etc.Evan Cheng2007-07-261-5/+5
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* Add selection DAG nodes for subreg insert/extract. PR1350Christopher Lamb2007-07-261-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40516 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from theDan Gohman2007-07-263-70/+35
| | | | | | | | x86 target, replacing them with the new alignment attributes on memory references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40504 91177308-0d34-0410-b5e6-96231b3b80d8
* Mac OS X x86-64 lower 4G address is not available.Evan Cheng2007-07-251-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40502 91177308-0d34-0410-b5e6-96231b3b80d8
* Mac OS X should use 0x90 to fill in gaps to satisfy function alignment ↵Evan Cheng2007-07-251-3/+12
| | | | | | requirements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40501 91177308-0d34-0410-b5e6-96231b3b80d8
* Functions with LinkOnce and weak linkage still need to be aligned. Doh.Evan Cheng2007-07-251-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40499 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't ignore the return value of AsmPrinter::doInitialization andDan Gohman2007-07-258-32/+23
| | | | | | | AsmPrinter::doFinalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix debug info and globals filled with zeros.Nick Lewycky2007-07-252-13/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40483 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanup:Anton Korobeynikov2007-07-251-1/+4
| | | | | | | | - Split EH and debug infiormation - Make DwarfWriter more verbose in some cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40481 91177308-0d34-0410-b5e6-96231b3b80d8
* Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.Dan Gohman2007-07-241-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40480 91177308-0d34-0410-b5e6-96231b3b80d8
* Use movaps to load a v4f32 build_vector of all-constant values into aDan Gohman2007-07-241-0/+9
| | | | | | | register instead of loading each element individually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40478 91177308-0d34-0410-b5e6-96231b3b80d8
* Heal EH handling stuff by emitting correct offsets to callee-saved registers.Anton Korobeynikov2007-07-241-1/+13
| | | | | | | Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40472 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some uses of dyn_cast to be uses of cast.Dan Gohman2007-07-231-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40443 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete the svn:executable property on these files, which aren't executable.Dan Gohman2007-07-235-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40441 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing SSE builtins:Bill Wendling2007-07-231-10/+38
| | | | | | | | | | | | __builtin_ia32_cvtss2si64 __builtin_ia32_cvttss2si64 __builtin_ia32_cvtsi642ss __builtin_ia32_cvtsd2si64 __builtin_ia32_cvttsd2si64 __builtin_ia32_cvtsi642sd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40411 91177308-0d34-0410-b5e6-96231b3b80d8
* No more noResults.Evan Cheng2007-07-2114-57/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
* Added -print-emitted-asm to print out JIT generated asm to cerr.Evan Cheng2007-07-208-17/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
* Because we promote SSE logical ops and loads to v2i64, we often end up generateEvan Cheng2007-07-201-11/+27
| | | | | | | | | | | | | code that cross integer / floating point domains (e.g. generate pxor / pand for logical ops on floating point value, movdqa to load / store floating point SSE values). Given that, it's better to use movaps instead of movdqa and movups instead of movdqu. They have the same latency but the "aps" variants are one byte shorter. If the domain crossing problem is a real performance issue, then we will have to fix it with dynamic programming based isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40076 91177308-0d34-0410-b5e6-96231b3b80d8
* Oops. These stores actually produce results.Evan Cheng2007-07-202-9/+9
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* Fix custom lowering of SSE FXOR.Evan Cheng2007-07-191-10/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40071 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG ↵Evan Cheng2007-07-191-12/+12
| | | | | | combiner may fold away the (bit_convert (load)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40070 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-1929-2510/+2629
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Only adjust esp around calls in presence of alloca.Evan Cheng2007-07-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40030 91177308-0d34-0410-b5e6-96231b3b80d8
* Only adjust esp around calls in presence of alloca.Evan Cheng2007-07-193-50/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40028 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if ↵Evan Cheng2007-07-181-13/+19
| | | | | | previous instruction updates esp, fold it in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40018 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement initial memory alignment awareness for SSE instructions. Vector loadsDan Gohman2007-07-181-59/+126
| | | | | | | | and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40015 91177308-0d34-0410-b5e6-96231b3b80d8
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-18240-0/+85965
alignment is equal to the stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40004 91177308-0d34-0410-b5e6-96231b3b80d8
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