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* Another fix to prevent debug info from affecting codegen. rdar://7797940Jim Grosbach2010-06-041-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
* more dbg_value adjustments so debug info doesn't affect codegenJim Grosbach2010-06-041-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typoJim Grosbach2010-06-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-043-31/+75
| | | | | | | | | | | | VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR node corresponds closely to REG_SEQUENCE but I couldn't use it here because its operands do not get legalized. That is pretty awful, but I guess it makes sense for other targets. Instead, I have added an ARM-specific version of BUILD_VECTOR that will have its operands properly legalized. This fixes the rest of Radar 7872877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the ARM load-store optimizer to deal with dbg_value instructions.Jim Grosbach2010-06-031-4/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
* Early implementation of tail call for ARM.Dale Johannesen2010-06-035-6/+371
| | | | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
* Add first pass at darwin tls compiler support.Eric Christopher2010-06-038-24/+168
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some already-fixed README entries.Eli Friedman2010-06-031-86/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105377 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove README entry which no longer compiles to something sane.Eli Friedman2010-06-031-56/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105376 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a fixed item, update a couple partially-fixed items.Eli Friedman2010-06-031-81/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105375 91177308-0d34-0410-b5e6-96231b3b80d8
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-026-23/+9
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-0219-50/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-028-43/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment so it doesn't include comments which are irrelevant to the x86Eli Friedman2010-06-021-9/+5
| | | | | | | | backend. Add a FIXME noting what can be fixed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105342 91177308-0d34-0410-b5e6-96231b3b80d8
* Use comments to document non-obvious code rather thanDan Gohman2010-06-021-0/+11
| | | | | | | mailing list archives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105341 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson2010-06-022-9/+10
| | | | | | | and tidy up the comment describing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace ARM's getCalleeSavedRegClasses with a simpler solutionRafael Espindola2010-06-022-94/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Rafael Espindola2010-06-022-56/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105325 91177308-0d34-0410-b5e6-96231b3b80d8
* cleanupRafael Espindola2010-06-0222-352/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove uses of getCalleeSavedRegClasses from outside theRafael Espindola2010-06-021-0/+19
| | | | | | | backends and removes the virtual declaration. With that out of the way I should be able to cleanup one backend at a time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105321 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; theEli Friedman2010-06-021-5/+7
| | | | | | | | | | | x86 backend currently doesn't know how to handle them. This doesn't really fix anything because LegalizeTypes doesn't know how to handle them either. We do get a better error message, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105305 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove outdated README entries.Eli Friedman2010-06-021-140/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105303 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the allocation of shadow space for the Win64 calling conventionDan Gohman2010-06-011-0/+6
| | | | | | | in X86FastISel. Patch by Jan Sjodin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105290 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor some SSE 2 unpack instructionsBruno Cardoso Lopes2010-06-011-66/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105276 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of 'load' nodes.Kalle Raiskila2010-06-011-8/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
* Some A9 load/store cleanupsAnton Korobeynikov2010-05-291-41/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105109 91177308-0d34-0410-b5e6-96231b3b80d8
* Some rough approximations for load/stores on A9Anton Korobeynikov2010-05-291-0/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105108 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON/VFP stuff can be issued only via Pipe1 on A9Anton Korobeynikov2010-05-291-87/+87
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105107 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some integer instruction itineraries for A9Anton Korobeynikov2010-05-291-0/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105106 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7193: if sibling call address can take a register, make sure there are ↵Evan Cheng2010-05-291-0/+18
| | | | | | enough registers available by counting inreg arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105092 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndicesJakob Stoklund Olesen2010-05-284-11/+9
| | | | | | | | | | were overspecified when inheriting sub-subregisters, for instance: R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit. This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
* Schedule high latency instructions for latency reduction even if they are ↵Evan Cheng2010-05-281-1/+19
| | | | | | not vfp / NEON instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment typos.Dale Johannesen2010-05-281-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105059 91177308-0d34-0410-b5e6-96231b3b80d8
* More SSE 1 & 2 merge, this time with logical instructionsBruno Cardoso Lopes2010-05-281-185/+98
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105014 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Add alias for movzx.Kevin Enderby2010-05-281-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105005 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Add alias for fwait.Kevin Enderby2010-05-281-0/+1
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* Fix the use of x86 control and debug registers so that the assertion failure inKevin Enderby2010-05-281-0/+28
| | | | | | | getX86RegNum() does not happen. Patch by Shantonu Sen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104994 91177308-0d34-0410-b5e6-96231b3b80d8
* correct retattrJim Grosbach2010-05-281-2/+2
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* Cosmetic cleanup. No functional change.Jim Grosbach2010-05-282-18/+18
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* make sure accesses to set up the jmpbuf don't get moved after it by the ↵Jim Grosbach2010-05-283-7/+10
| | | | | | scheduler. Add a missing \n. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the cc_out operand for t2RSBrs instructions. I missed this when I changedBob Wilson2010-05-281-2/+2
| | | | | | | | the instruction class for t2RSB to add that operand in svn r104582. Radar 8033757. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the saved stack pointer in the sjlj function context following eitherJim Grosbach2010-05-275-19/+10
| | | | | | | | an alloca() or an llvm.stackrestore(). rdar://8031573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
* Use report_fatal_error, not llvm_unreachable.Evan Cheng2010-05-271-1/+1
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* back out 104862/104869. Can reuse stacksave after all. Very cool.Jim Grosbach2010-05-272-9/+0
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* llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.Evan Cheng2010-05-271-18/+2
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* MC/X86: Add aliases for Jcc variants.Kevin Enderby2010-05-271-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104890 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' casesBob Wilson2010-05-271-11/+17
| | | | | | | | should fall through to the 'H' case, but instead 'Q' was falling through to 'R' so that it would do the wrong thing for a big-endian ARM target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark some math lib intrinsic nodes Legal on SSE4.1.Dale Johannesen2010-05-271-0/+11
| | | | | | | | No functional effect as these nodes are not generated yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104879 91177308-0d34-0410-b5e6-96231b3b80d8
* FastISel doesn't yet handle callee-pop functions.Dan Gohman2010-05-274-25/+33
| | | | | | | To support this, move IsCalleePop from X86ISelLowering to X86Subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
* add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EHJim Grosbach2010-05-272-0/+9
| | | | | | to update the jmpbuf in the presence of VLAs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
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