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* Rename a parameter to avoid confusion with a local variableMatt Beaumont-Gay2010-11-101-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the warning about the register list not being in ascending order only once.Bill Wendling2010-11-091-5/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
* s/std::vector/SmallVector/Bill Wendling2010-11-091-12/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete the allocated vector.Bill Wendling2010-11-091-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
* Define the subtarget feature for the architecture version,Bob Wilson2010-11-091-15/+40
| | | | | | | as derived from the target triple. This is important for enabling features that are implied based on the architecture version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson2010-11-091-2/+2
| | | | | | | | | It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
* Two types of instructions have register lists:Bill Wendling2010-11-091-56/+32
| | | | | | | | | | | | * LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach2010-11-094-17/+42
| | | | | | help in MC'izing the references that use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle ARM constant pool values that need an explicit reference to the '.'Jim Grosbach2010-11-091-1/+9
| | | | | | pseudo-label. (TLS stuff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
* add a case we fail to devirt.Chris Lattner2010-11-091-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118608 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2010-11-091-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
* Further MCize ARM constant pool values. This allows basic PIC references forJim Grosbach2010-11-091-67/+83
| | | | | | object file emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.Jim Grosbach2010-11-091-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
* For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach2010-11-091-0/+3
| | | | | | a left shift by zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM .word data fixups don't need an adjustment.Jim Grosbach2010-11-091-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix trailing whitespace and style, no functionality changeBruno Cardoso Lopes2010-11-091-170/+95
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-093-1/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach2010-11-092-10/+36
| | | | | | | | | | | | | | | | constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling2010-11-092-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
* Get the register and count from the register list operands.Bill Wendling2010-11-081-8/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
* reglist has two operands.Bill Wendling2010-11-081-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
* The "addRegListOperands()" function returns the start register and the totalBill Wendling2010-11-081-15/+21
| | | | | | | number of registers in the list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson2010-11-083-24/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka ↵Bruno Cardoso Lopes2010-11-083-12/+22
| | | | | | (ahatanaka@mips.com) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
* Add "write back" bit encoding.Bill Wendling2010-11-081-8/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR8211Bruno Cardoso Lopes2010-11-081-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118445 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding working version of assembly parser for the MBlaze backendWesley Peck2010-11-0825-810/+498
| | | | | | | Major cleanup of whitespace and formatting issues in MBlaze backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118434 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 118422 in search of bot verdancy.Dale Johannesen2010-11-082-78/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
* Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim2010-11-082-10/+78
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
* Complete listing of ARM/MC/ELF relocation enumsJason W Kim2010-11-081-3/+134
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
* Add generating function declaration for PTXChe-Liang Chiou2010-11-082-11/+129
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118398 91177308-0d34-0410-b5e6-96231b3b80d8
* Add physical register counting functionsChe-Liang Chiou2010-11-086-0/+176
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118397 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a dummy PTXMCAsmStreamer classChe-Liang Chiou2010-11-084-0/+588
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118396 91177308-0d34-0410-b5e6-96231b3b80d8
* Make RegList an ASM operand so that TableGen will generate code for it. This isBill Wendling2010-11-081-2/+7
| | | | | | | an initial implementation and may change once reglists are fully fleshed out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert.Bill Wendling2010-11-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a README item: when doing a comparison with the resultDuncan Sands2010-11-071-12/+0
| | | | | | | | | of a select instruction, see if doing the compare with the true and false values of the select gives the same result. If so, that can be used as the value of the comparison. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118378 91177308-0d34-0410-b5e6-96231b3b80d8
* In this context, a reglist is a reg.Bill Wendling2010-11-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
* implement aliases for div/idiv that have an explicit A register operand,Chris Lattner2010-11-061-0/+20
| | | | | | | implementing rdar://8431864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118364 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
* add aliases for movs between seg registers and mem. There are multipleChris Lattner2010-11-061-0/+5
| | | | | | | | | | | different forms of this instruction (movw/movl/movq) which we reported as being ambiguous. Since they all do the same thing, gas just picks the one with the shortest encoding. Follow its lead here. This implements rdar://8208615 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118362 91177308-0d34-0410-b5e6-96231b3b80d8
* move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file.Chris Lattner2010-11-062-10/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118361 91177308-0d34-0410-b5e6-96231b3b80d8
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
* work-in-progressChris Lattner2010-11-061-7/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118358 91177308-0d34-0410-b5e6-96231b3b80d8
* General cleanup:Bill Wendling2010-11-061-36/+21
| | | | | | | | - Make ARMOperand a class so that some things are internal to the class. - Reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
* go to great lengths to work around a GAS bug my previous patchChris Lattner2010-11-062-8/+8
| | | | | | | | | | | | | | | | | exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
* rework the rotate-by-1 instructions to be defined like theChris Lattner2010-11-063-25/+46
| | | | | | | | | | | | | | shift-by-1 instructions, where the asmstring doesn't contain the implicit 1. It turns out that a bunch of these rotate instructions were completely broken because they used 1 instead of $1. This fixes assembly mismatches on "rclb $1, %bl" and friends, where we used to generate the 3 byte form, we now generate the proper 2-byte form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118355 91177308-0d34-0410-b5e6-96231b3b80d8
* change the fp comparison instructions to not have %st0 explicitlyChris Lattner2010-11-062-12/+9
| | | | | | | | | listed in its asm string, for consistency with the other similar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118354 91177308-0d34-0410-b5e6-96231b3b80d8
* move the plethora of fp stack aliases to the .td file.Chris Lattner2010-11-062-39/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118353 91177308-0d34-0410-b5e6-96231b3b80d8
* add (and document) the ability for alias results to haveChris Lattner2010-11-062-13/+16
| | | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118352 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RegList (register list) object to ARMOperand. It will be used soon to holdBill Wendling2010-11-061-1/+38
| | | | | | | | (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
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