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* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-133-3/+46
| | | | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-131-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175067 91177308-0d34-0410-b5e6-96231b3b80d8
* Add registration for PPC-specific passes to allow the IR to be dumpedKrzysztof Parzyszek2013-02-133-3/+41
| | | | | | via -print-after-all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175058 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-131-0/+8
| | | | | | | | | | | This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175057 91177308-0d34-0410-b5e6-96231b3b80d8
* Make jumptables work for -staticReed Kotler2013-02-131-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky2013-02-131-0/+10
| | | | | | since a caller uses preserved registers across the call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-1/+1
| | | | | | assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175036 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit. Fixed typo.David Peixotto2013-02-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175020 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-20/+123
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Disable vector registersJustin Holewinski2013-02-1217-1997/+1274
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix regression with shadow array sampler on pre-SI GPUs.Michel Danzer2013-02-121-1/+1
| | | | | | | | | | | | | | | | 'R600/SI: Use proper instructions for array/shadow samplers.' removed two cases from TEX_SHADOW. Vincent Lejeune reported on IRC that this broke some shadow array piglit tests with the r600g driver. Reinstating the removed cases should fix this, and still works with radeonsi as well. I will follow up with some lit tests which would have caught the regression. NOTE: This is a candidate for the Mesa stable branch. Tested-by: Vincent Lejeune <vljn@ovi.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174963 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-121-0/+33
| | | | | | | | | A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174933 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-1/+37
| | | | | | | | | | | | | | | Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174929 91177308-0d34-0410-b5e6-96231b3b80d8
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-4/+2
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174920 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Expand pseudo instructions before they are emitted inAkira Hatanaka2013-02-111-11/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | MipsCodeEmitter.cpp. JALR and NOP are expanded by function emitPseudoExpansionLowering, which is not called when the old JIT is used. This fixes the following tests which have been failing on llvm-mips-linux builder: LLVM :: ExecutionEngine__2003-01-04-LoopTest.ll LLVM :: ExecutionEngine__2003-05-06-LivenessClobber.ll LLVM :: ExecutionEngine__2003-06-04-bzip2-bug.ll LLVM :: ExecutionEngine__2005-12-02-TailCallBug.ll LLVM :: ExecutionEngine__2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll LLVM :: ExecutionEngine__hello2.ll LLVM :: ExecutionEngine__stubs.ll LLVM :: ExecutionEngine__test-branch.ll LLVM :: ExecutionEngine__test-call.ll LLVM :: ExecutionEngine__test-common-symbols.ll LLVM :: ExecutionEngine__test-loadstore.ll LLVM :: ExecutionEngine__test-loop.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174912 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix indentation.Akira Hatanaka2013-02-111-41/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174907 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-114-382/+1470
| | | | | | | | - variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174904 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement HexagonInstrInfo::analyzeCompare.Krzysztof Parzyszek2013-02-112-0/+86
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174901 91177308-0d34-0410-b5e6-96231b3b80d8
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-4/+4
| | | | | | *added file for test cases for i386 intel syntax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use V_ADD_F32 instead of V_MOV_B32 for clamp/neg/abs modifiers.Michel Danzer2013-02-111-15/+9
| | | | | | | | | | | | | | The modifiers don't seem to have any effect with V_MOV_B32, supposedly it's meant to just move bits untouched. Fixes 46 piglit tests with radeonsi, though unfortunately 11 of those had just regressed because they started using the clamp modifier. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174890 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: fix build on some MSVC versionsTim Northover2013-02-111-3/+3
| | | | | | | | | | | | | | | This does two things: It removes a call to abs() which may have "long long" parameter on Windows, which is not necessarily available in C++03. It also corrects the signedness of Amount, which was relying on implementation-defined conversions previously. Code was already tested (albeit in an implemnetation defined way) so no extra tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174885 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: Simplify logic in deciding whether bfi is validTim Northover2013-02-111-6/+1
| | | | | | | | Previous code had a confusing comment which was mostly an implementation detail. This condition corresponds to "lsb up to register width" and "width not ridiculous". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174877 91177308-0d34-0410-b5e6-96231b3b80d8
* Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover2013-02-112-18/+218
| | | | | | | | | This gives a DiagnosticType to all AsmOperands in sight. This replaces all "invalid operand" diagnostics with something more specific. The messages given should still be sufficiently vague that they're not usually actively misleading when LLVM guesses your instruction incorrectly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174871 91177308-0d34-0410-b5e6-96231b3b80d8
* Currently, codegen may spent some time in SDISel passes even if an entireEvan Cheng2013-02-111-0/+74
| | | | | | | | | | | | | | | function is successfully handled by fast-isel. That's because function arguments are *always* handled by SDISel. Introduce FastLowerArguments to allow each target to provide hook to handle formal argument lowering. As a proof-of-concept, add ARMFastIsel::FastLowerArguments to handle functions with 4 or fewer scalar integer (i8, i16, or i32) arguments. It completely eliminates the need for SDISel for trivial functions. rdar://13163905 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174855 91177308-0d34-0410-b5e6-96231b3b80d8
* Spelling correctionJoel Jones2013-02-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174852 91177308-0d34-0410-b5e6-96231b3b80d8
* Test Commit - Remove some trailing whitespace in R600Instructions.tdVincent Lejeune2013-02-101-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174839 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Make address space errors more explicit (llvm_unreachable -> ↵Justin Holewinski2013-02-091-1/+2
| | | | | | report_fatal_error) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174808 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Dump the function name when TargetLowering::LowerCall() failsTom Stellard2013-02-081-0/+5
| | | | | | | | Also output a more useful error message. NOTE: This is a candidate for the Mesa stable branch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174763 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: rework flow creation in the structurizer v2Tom Stellard2013-02-081-177/+195
| | | | | | | | | | | | | This fixes a couple of bugs and incorrect assumptions, in total four more piglit tests now pass. v2: fix small bug in the dominator updating Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174762 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: fix loop analyses in the structurizerTom Stellard2013-02-081-113/+183
| | | | | | | | | | | Patch by: Christian König Intersecting loop handling was wrong. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174761 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: fix PHI value adding in the structurizerTom Stellard2013-02-081-65/+81
| | | | | | | | | | | Otherwise we sometimes produce invalid code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174760 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler2013-02-082-0/+21
| | | | | | | | | | | | same so we put in the comment field an indicator when we think we are emitting the 16 bit version. For the direct object emitter, the difference is important as well as for other passes which need an accurate count of program size. There will be other similar putbacks to this for various instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
* Refine fix to bug 15041.Bill Schmidt2013-02-081-18/+17
| | | | | | | | | | | Thanks to help from Nadav and Hal, I have a more reasonable (and even correct!) approach. This specifically penalizes the insertelement and extractelement operations for the performance hit that will occur on PowerPC processors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174725 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM cost model: Address computation in vector mem ops not freeArnold Schwaighofer2013-02-081-2/+11
| | | | | | | | | | | | | | | Adds a function to target transform info to query for the cost of address computation. The cost model analysis pass now also queries this interface. The code in LoopVectorize adds the cost of address computation as part of the memory instruction cost calculation. Only there, we know whether the instruction will be scalarized or not. Increase the penality for inserting in to D registers on swift. This becomes necessary because we now always assume that address computation has a cost and three is a closer value to the architecture. radar://13097204 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174713 91177308-0d34-0410-b5e6-96231b3b80d8
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-083-10/+90
| | | | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make Filler a class and reduce indentation.Akira Hatanaka2013-02-071-34/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174666 91177308-0d34-0410-b5e6-96231b3b80d8
* Constrain PowerPC autovectorization to fix bug 15041.Bill Schmidt2013-02-071-0/+19
| | | | | | | | | | | | | | Certain vector operations don't vectorize well with the current PowerPC implementation. Element insert/extract performs poorly without VSX support because Altivec requires going through memory. SREM, UREM, and VSELECT all produce bad scalar code. There's a lot of work to do for the cost model before autovectorization will be tuned well, and this is not an attempt to address the larger problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174660 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka2013-02-073-3/+14
| | | | | | | | | | Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: cleanup VGPR encodingTom Stellard2013-02-075-178/+16
| | | | | | | | | | | Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174656 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Handle VGPR64 destination in copyPhysReg().Tom Stellard2013-02-071-1/+9
| | | | | | | | | | | Allows nexuiz to run with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174655 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for mul.Tom Stellard2013-02-071-0/+4
| | | | | | | | | | | 20 more little piglits with radeonsi. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174654 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: simplify and fix SMRD encodingTom Stellard2013-02-076-154/+70
| | | | | | | | | | | The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174653 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: add proper 64bit immediate support v2Tom Stellard2013-02-073-12/+18
| | | | | | | | | | | v2: rebased on current upstream Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174652 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add an explicit default processorTom Stellard2013-02-071-0/+1
| | | | | | | | | | | This is for the case when no processor is passed to the backend. This prevents the '' is not a recognized processor for this target (ignoring processor) warning from being generated by clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174651 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use proper instructions for array/shadow samplers.Tom Stellard2013-02-072-4/+54
| | | | | | | | | Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174634 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Make sample intrinsic address parameter type overloaded.Tom Stellard2013-02-073-22/+38
| | | | | | | | | | | | | | Handle vectors of 1 to 16 integers. Change the intrinsic names to prevent the wrong one from being selected at runtime due to the overloading. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174633 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add basic support for more integer vector types.Tom Stellard2013-02-075-11/+110
| | | | | | | | | | | | | | v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM cost model: Add costs for vector selectsArnold Schwaighofer2013-02-071-0/+15
| | | | | | | | Vector selects are cheap on NEON. They get lowered to a vbsl instruction. radar://13158753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174631 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for flog2Michel Danzer2013-02-071-1/+3
| | | | | | | | 22 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174615 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Consolidate sub register indices.Tom Stellard2013-02-078-93/+73
| | | | | | | | | | | Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174610 91177308-0d34-0410-b5e6-96231b3b80d8
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