aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* trailing whitespaceJim Grosbach2010-11-011-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
* The T2 extract/pack instructions are only valid in Thumb2 mode. Mark theJim Grosbach2010-11-011-12/+14
| | | | | | patterns as such git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
* Move instruction encoding bits into the parent class and remove the temporaryBill Wendling2010-11-012-273/+224
| | | | | | | | *_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117906 91177308-0d34-0410-b5e6-96231b3b80d8
* "mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner2010-11-011-0/+6
| | | | | | | must be 8 bits. Support this memory form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117902 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement enough of the missing instalias support to getChris Lattner2010-11-012-3/+33
| | | | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117901 91177308-0d34-0410-b5e6-96231b3b80d8
* make the asm matcher emitter reject instructions that have commentsChris Lattner2010-11-011-2/+2
| | | | | | | | in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117897 91177308-0d34-0410-b5e6-96231b3b80d8
* reject instructions that contain a \n in their asmstring. MarkChris Lattner2010-11-012-8/+13
| | | | | | | | various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117884 91177308-0d34-0410-b5e6-96231b3b80d8
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-312-0/+6
| | | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
* two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner2010-10-314-9/+19
| | | | | | | | and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
* reapply r117858 with apparent editor malfunction fixed (somehow I Chris Lattner2010-10-315-11/+21
| | | | | | | got a dulicated line). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
* revert r117858 while I check out a failure I missed.Chris Lattner2010-10-315-21/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
* the asm matcher can't handle operands with modifiers (like ${foo:bar}).Chris Lattner2010-10-315-11/+21
| | | | | | | | | | | | Instead of silently ignoring these instructions, emit a hard error and force the target author to either refactor the target or mark the instruction 'isCodeGenOnly'. Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are doing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
* sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner2010-10-311-0/+14
| | | | | | | how the push/pop mnemonic aliases are wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117857 91177308-0d34-0410-b5e6-96231b3b80d8
* Factorize the duplicated logic for choosing the right argumentDuncan Sands2010-10-314-56/+36
| | | | | | | | calling convention out of the fast and normal ISel files, and into the calling convention TD file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117856 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands2010-10-311-16/+1
| | | | | | | | which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117855 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we have a legal type (and simple) before continuing.Eric Christopher2010-10-301-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117848 91177308-0d34-0410-b5e6-96231b3b80d8
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-2/+2
| | | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-302-14/+20
| | | | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117830 91177308-0d34-0410-b5e6-96231b3b80d8
* really zap alias.Chris Lattner2010-10-301-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117824 91177308-0d34-0410-b5e6-96231b3b80d8
* move fcompi alias to .td file and zap some useless code.Chris Lattner2010-10-302-11/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117823 91177308-0d34-0410-b5e6-96231b3b80d8
* move rep aliases to td fileChris Lattner2010-10-302-5/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117822 91177308-0d34-0410-b5e6-96231b3b80d8
* move sal aliases to .td file.Chris Lattner2010-10-302-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117821 91177308-0d34-0410-b5e6-96231b3b80d8
* fix an encoding mismatch where "sal %eax, 1" was not using the short encodingChris Lattner2010-10-301-1/+1
| | | | | | | for shl. Caught by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
* move a bunch more aliases from .cpp -> .td file.Chris Lattner2010-10-302-22/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117819 91177308-0d34-0410-b5e6-96231b3b80d8
* move cmov aliases to .td file.Chris Lattner2010-10-302-49/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117818 91177308-0d34-0410-b5e6-96231b3b80d8
* move setcc and jcc aliases from .cpp to .tdChris Lattner2010-10-302-14/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117817 91177308-0d34-0410-b5e6-96231b3b80d8
* move some code.Chris Lattner2010-10-301-33/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117816 91177308-0d34-0410-b5e6-96231b3b80d8
* implement (and document!) the first kind of MC assembler alias, which Chris Lattner2010-10-302-15/+23
| | | | | | | | just remaps one mnemonic to another. Convert a few of the X86 aliases from .cpp to .td code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117815 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FIXME.Jim Grosbach2010-10-301-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117787 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up comments.Jim Grosbach2010-10-301-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117785 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2010-10-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117782 91177308-0d34-0410-b5e6-96231b3b80d8
* stay out of the reserved namespaceChris Lattner2010-10-301-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117773 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify this code.Chris Lattner2010-10-301-8/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
* split MaybeParseRegister into its two logical uses, eliminating malloc+free ↵Chris Lattner2010-10-301-35/+38
| | | | | | traffic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid re-evaluating MI.getNumOperands() every iteration of the loop.Jim Grosbach2010-10-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117766 91177308-0d34-0410-b5e6-96231b3b80d8
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-305-131/+61
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-304-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-3/+9
| | | | | | | conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hard tab characters.Jim Grosbach2010-10-291-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117740 91177308-0d34-0410-b5e6-96231b3b80d8
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-293-3/+3
| | | | | | encoder functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-293-4/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
* add FIXMEJim Grosbach2010-10-291-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117718 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-294-45/+32
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117714 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle comparison values we already have - this fixes the consumer-typesetEric Christopher2010-10-291-4/+65
| | | | | | | failure for llvm-gcc on arm fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117710 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need toJim Grosbach2010-10-291-55/+0
| | | | | | handle it in the asm lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo.Jim Grosbach2010-10-291-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117703 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj ↵Jim Grosbach2010-10-292-20/+25
| | | | | | pseudos and a FIXME for TLS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117702 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM mode LDREX*/STREX* binary encodings.Jim Grosbach2010-10-292-18/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117695 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-06 17:30:42 +0000