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* Resolve bug 2947: vararg-marked functions must spill registers R3-R79 to stackScott Michel2008-10-302-114/+69
| | | | | | | | | | so that va_start/va_arg/et.al. will walk arguments correctly for Cell SPU. N.B.: Because neither clang nor llvm-gcc-4.2 can be built for CellSPU, this is still unexorcised code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58415 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct way to handle CONSTPOOL_ENTRY instructions.Evan Cheng2008-10-294-37/+82
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58409 91177308-0d34-0410-b5e6-96231b3b80d8
* Add debugging support.Evan Cheng2008-10-292-1/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58408 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PEXTRQ encodingNate Begeman2008-10-291-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58403 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RM pseudoreg for the rounding mode, whichDale Johannesen2008-10-294-165/+200
| | | | | | | | | | | | | | | | | | | allows ppcf128->int conversion to work with DeadInstructionElimination. This is now turned off but RM is harmless. It does not do a complete job of modeling the rounding mode. Revert marking MFCR as using all 7 CR subregisters; while correct, this caused the problem in PR 2964, plus the local RA crash noted in the comments. This was needed to make DeadInstructionElimination, but as we are not running that, it is backed out for now. Eventually it should go back in and the other problems fixed where they're broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for constant islands in the ARM JIT.Jim Grosbach2008-10-282-2/+49
| | | | | | | | | | | | | | | | | Since the ARM constant pool handling supercedes the standard LLVM constant pool entirely, the JIT emitter does not allocate space for the constants, nor initialize the memory. The constant pool is considered part of the instruction stream. Likewise, when resolving relocations into the constant pool, a hook into the target back end is used to resolve from the constant ID# to the address where the constant is stored. For now, the support in the ARM emitter is limited to 32-bit integer. Future patches will expand this to the full range of constants necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58338 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix darwin ppc llvm-gcc build breakage: interceptDuncan Sands2008-10-281-5/+7
| | | | | | | | | | | ppcf128 to i32 conversion and expand it into a code sequence like in LegalizeDAG. This needs custom ppc lowering of FP_ROUND_INREG, so turn that on and make it work with LegalizeTypes. Probably PPC should simply custom lower the original conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58329 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a nasty miscompilation of 176.gcc on linux/x86 where we synthesizedChris Lattner2008-10-281-4/+9
| | | | | | | | | | | | | a memset using 16-byte XMM stores, but where the stack realignment code didn't work. Until it does (PR2962) disable use of xmm regs in memcpy and memset formation for linux and other targets with insufficiently aligned stacks. This is part of PR2888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58317 91177308-0d34-0410-b5e6-96231b3b80d8
* Have TableGen emit setSubgraphColor calls under control of a -gen-debugDavid Greene2008-10-279-9/+9
| | | | | | | | | flag. Then in a debugger developers can set breakpoints at these calls to see waht is about to be selected and what the resulting subgraph looks like. This really helps when debugging instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
* For now, don't split live intervals around x87 stack register barriers. ↵Evan Cheng2008-10-273-0/+17
| | | | | | FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the code that adds the DeadMachineInstructionElimPass fromDan Gohman2008-10-251-0/+5
| | | | | | | | | | | | | target-independent code to target-specific code. This prevents it from running on targets that aren't using fast-isel. In addition to saving compile time, this addresses the problem that not all targets are prepared for it. In order to use this pass, all instructions must declare all their fixed uses and defs of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58144 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for allocation of TLS variables in the JIT. Allocation of a globalNicolas Geoffray2008-10-252-1/+20
| | | | | | | | | | variable is moved to the execution engine. The JIT calls the TargetJITInfo to allocate thread local storage. Currently, only linux/x86 knows how to allocate thread local global variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58142 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate code for TLS instructions.Nicolas Geoffray2008-10-253-4/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58141 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: lib/Target/ARM/AsmPrinter/CMakeLists.txt added.Oscar Fuentes2008-10-251-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58133 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark MFCR as reading all condition code registers.Dale Johannesen2008-10-241-0/+2
| | | | | | | | | Prevents some more overzealous deletions (mostly in AltiVec code). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58121 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite logic to figure out whether LR needs toDale Johannesen2008-10-242-32/+34
| | | | | | | | | | be saved/restored in the prolog/epilog. We need to do this iff something in the function stores into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58116 91177308-0d34-0410-b5e6-96231b3b80d8
* move the note to the correct READMEEdwin Török2008-10-242-95/+97
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58104 91177308-0d34-0410-b5e6-96231b3b80d8
* add note about va_arg code on x86 and x86-64Edwin Török2008-10-241-0/+94
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58103 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix translateX86CC: if SetCCOpcode is SETULE andDuncan Sands2008-10-241-13/+10
| | | | | | | | | | | | | | | LHS is a foldable load, then LHS and RHS are swapped and SetCCOpcode is changed to SETUGT. But the later code is expecting operands to be the wrong way round for SETUGT, but they are not in this case, resulting in an inverted compare. The solution is to move the load normalization before the correction for SETUGT. This bug was tickled by LegalizeTypes which happened to legalize the testcase slightly differently to LegalizeDAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58092 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix constant-offset emission for x86-64 absolute addresses. ThisDan Gohman2008-10-242-11/+22
| | | | | | | | fixes a bunch of test-suite JIT failures on x86-64 in -relocation-model=static mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58066 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark defs and uses of CTR and LR correctly.Dale Johannesen2008-10-232-11/+30
| | | | | | | | | | Prevents DeadMachineInstructionElim from thinking things like MTCTR are dead (fixes massive testsuite breakage at -O0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58043 91177308-0d34-0410-b5e6-96231b3b80d8
* remove extraneous #ifdef'sJim Grosbach2008-10-221-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58006 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove allocation of unused stack slot.Dale Johannesen2008-10-221-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57987 91177308-0d34-0410-b5e6-96231b3b80d8
* Get this working with LegalizeTypes: (1) don'tDuncan Sands2008-10-221-5/+9
| | | | | | | | | | assume that i64 has been turned into a BUILD_PAIR node (when called from LegalizeTypes this hasn't happened yet) and don't use a vector shuffle mask with an illegal element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57972 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR2907 by digging through constant expressions to find FP constants thatChris Lattner2008-10-221-42/+63
| | | | | | | are their operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57956 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: Turned some libraries into partially linked objects. CorrectedOscar Fuentes2008-10-223-3/+3
| | | | | | | names of LLVMCore and ARMCodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57943 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust comments for pedantic satisfaction.Dale Johannesen2008-10-221-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57940 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments to explain uint64->f64 algorithm,Dale Johannesen2008-10-211-0/+35
| | | | | | | | well, sort of. (Algorithm by Ian Ollmann.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57932 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an SSE2 algorithm for uint64->f64 conversion.Dale Johannesen2008-10-212-2/+70
| | | | | | | | | | | | The same one Apple gcc uses, faster. Also gets the extreme case in gcc.c-torture/execute/ieee/rbug.c correct which we weren't before; this is not sufficient to get the test to pass though, there is another bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57926 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the optimized FCMP_OEQ/FCMP_UNE code for x86 fast-isel.Dan Gohman2008-10-211-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57915 91177308-0d34-0410-b5e6-96231b3b80d8
* use pre-UAL mnemonics for push/pop for compilaton callback functionJim Grosbach2008-10-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57911 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable constant-offset folding for PowerPC, as the PowerPC targetDan Gohman2008-10-212-0/+8
| | | | | | | isn't yet prepared for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57886 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't create TargetGlobalAddress nodes with offsets that don't fitDan Gohman2008-10-211-1/+1
| | | | | | | | | | | | | | | in the 32-bit signed offset field of addresses. Even though this may be intended, some linkers refuse to relocate code where the relocated address computation overflows. Also, fix the sign-extension of constant offsets to use the actual pointer size, rather than the size of the GlobalAddress node, which may be different, for example on x86-64 where MVT::i32 is used when the address is being fit into the 32-bit displacement field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57885 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimized FCMP_OEQ and FCMP_UNE for x86.Dan Gohman2008-10-213-86/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
* When the coalescer is doing rematerializing, have it removeDan Gohman2008-10-211-3/+8
| | | | | | | | | | | | | | | | | | | | | the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57872 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the stub and callback code to handle lazy compilation. The stubJim Grosbach2008-10-201-62/+90
| | | | | | | | | | | | is re-written by the callback to branch directly to the compiled code in future invocations. Added back in range-based memory permission functions for the updating of the stub on Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57846 91177308-0d34-0410-b5e6-96231b3b80d8
* Have X86 custom lowering for LegalizeTypes useDuncan Sands2008-10-201-10/+12
| | | | | | | | | | | | | | LowerOperation if it doesn't know what else to do. This methods should probably be factorized some, but this is good enough for the moment. Have LowerATOMIC_BINARY_64 use EXTRACT_ELEMENT rather than assuming the operand is a BUILD_PAIR (if it is then getNode will automagically simplify the EXTRACT_ELEMENT). This way LowerATOMIC_BINARY_64 usable from LegalizeTypes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57831 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-1812-70/+94
| | | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
* This is now partly done.Dan Gohman2008-10-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57734 91177308-0d34-0410-b5e6-96231b3b80d8
* This is done.Dan Gohman2008-10-171-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57733 91177308-0d34-0410-b5e6-96231b3b80d8
* Add implicit defs of XMM8 to XMM15 on 32-bit call instructions. While this ↵Evan Cheng2008-10-171-1/+2
| | | | | | is not technically true, it tells tblgen that these instructions "clobber" the entire XMM register file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57723 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for 128 bit inputs on both x86-64 and x86-32.Chris Lattner2008-10-171-9/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57709 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where the x86 backend would reject 64-bit r constraints whenChris Lattner2008-10-171-1/+1
| | | | | | | | in 32-bit mode instead of assigning a register pair. This has nothing to do with PR2356, but I happened to notice it while working on it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57704 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions ↵Evan Cheng2008-10-172-5/+17
| | | | | | except they do not have any operands. The RegModRM byte is encoded with register number 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57692 91177308-0d34-0410-b5e6-96231b3b80d8
* getX86RegNum has long been moved to X86RegisterInfo.Evan Cheng2008-10-171-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57691 91177308-0d34-0410-b5e6-96231b3b80d8
* add some simple hacky long double support for the CBE. ThisChris Lattner2008-10-171-5/+15
| | | | | | | | should work for intel long double, but ppc long double aborts in convert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57672 91177308-0d34-0410-b5e6-96231b3b80d8
* Fun x86 encoding tricks: when adding an immediate value of 128,Dan Gohman2008-10-172-8/+26
| | | | | | | | | | | | | | use a SUB instruction instead of an ADD, because -128 can be encoded in an 8-bit signed immediate field, while +128 can't be. This avoids the need for a 32-bit immediate field in this case. A similar optimization applies to 64-bit adds with 0x80000000, with the 32-bit signed immediate field. To support this, teach tablegen how to handle 64-bit constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57663 91177308-0d34-0410-b5e6-96231b3b80d8
* Define patterns for shld and shrd that match immediateDan Gohman2008-10-173-20/+136
| | | | | | | | | | | | | | | | | | | shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
* Trim #includes.Dan Gohman2008-10-1610-23/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typo noticed by sdtChris Lattner2008-10-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57644 91177308-0d34-0410-b5e6-96231b3b80d8
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