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* Fix compile warnings.Richard Osborne2008-11-072-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58840 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU: Ensure that C strings are always put in the .rodata sectionScott Michel2008-11-071-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58839 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore backend.Richard Osborne2008-11-0725-0/+4954
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58838 91177308-0d34-0410-b5e6-96231b3b80d8
* Jump table JIT support. Work in progress.Evan Cheng2008-11-076-76/+192
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach CellSPU about ELF sections and new section emitter classes.Scott Michel2008-11-073-35/+46
| | | | | | | NB: This is likely to need more work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58832 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode misc arithmetic instructions.Evan Cheng2008-11-074-14/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58828 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode extend instructions; more clean up.Evan Cheng2008-11-064-75/+142
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58818 91177308-0d34-0410-b5e6-96231b3b80d8
* - Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.Evan Cheng2008-11-064-76/+48
| | | | | | | | - Consolidate instruction formats. - Other clean up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58808 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 ↵Evan Cheng2008-11-066-234/+228
| | | | | | encoding bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
* Widening cleanupMon P Wang2008-11-061-4/+2
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* Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.Evan Cheng2008-11-063-64/+101
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* Fix so_imm encoding bug; add support for MOVi2pieces.Evan Cheng2008-11-063-16/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58790 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of multiple instructions with 3 src operands; also handle ↵Evan Cheng2008-11-064-77/+96
| | | | | | smmul, smmla, and smmls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58789 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode pic load / store instructions; fix some encoding bugs.Evan Cheng2008-11-053-89/+153
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58780 91177308-0d34-0410-b5e6-96231b3b80d8
* Restructure ARM code emitter to use instruction formats instead of ↵Evan Cheng2008-11-055-285/+302
| | | | | | addressing modes to determine how to encode instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58764 91177308-0d34-0410-b5e6-96231b3b80d8
* Reintroduce a comment that was removed with the AddToISelQueueDan Gohman2008-11-051-0/+1
| | | | | | | changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58760 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit, add Makefile for XCore target, more to follow.Richard Osborne2008-11-051-0/+21
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* Add more vector move low and zero-extend patterns.Evan Cheng2008-11-051-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58752 91177308-0d34-0410-b5e6-96231b3b80d8
* Indentation.Evan Cheng2008-11-051-1/+1
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* Eliminate the ISel priority queue, which used the topological order for aDan Gohman2008-11-058-165/+30
| | | | | | | | | | | | | | | | | | | | | | | | | priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
* Use getTargetConstant instead of getConstant for nodes that should not be ↵Dan Gohman2008-11-051-8/+8
| | | | | | | | | visited by isel and potentially forced into registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58747 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isGVLazyPtr to isGVNonLazyPtr relocation. This represents Mac OS XEvan Cheng2008-11-053-22/+23
| | | | | | | indirect gv reference. Please don't call it lazy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58746 91177308-0d34-0410-b5e6-96231b3b80d8
* Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.Evan Cheng2008-11-041-4/+0
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* Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with ↵Evan Cheng2008-11-041-9/+12
| | | | | | legalizetypes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58714 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug output tweak.Evan Cheng2008-11-041-2/+2
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* LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.Evan Cheng2008-11-041-1/+0
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* For some targets, it's not possible to place GVs in the same memory buffer ↵Evan Cheng2008-11-041-0/+11
| | | | | | | | | as the MachineCodeEmitter allocated memory. Code and data has different read / write / execution privilege requirements. This is a short term workaround. The current solution is for the JIT memory manager to manage code and data memory separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58688 91177308-0d34-0410-b5e6-96231b3b80d8
* Stylistic change.Evan Cheng2008-11-041-2/+2
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* Handle ARM machine constantpool entries.Evan Cheng2008-11-045-20/+77
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* The ANDMask node folds to a constant, and isn't the node that needs toDan Gohman2008-11-031-2/+2
| | | | | | | | have its node id set. The new and and shift nodes are the nodes that need the IDs. This fixes PR2982. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58655 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a dead switch statement.Evan Cheng2008-11-031-17/+0
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* Minor code restructuring. No functionality change.Evan Cheng2008-11-031-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58643 91177308-0d34-0410-b5e6-96231b3b80d8
* Add binary encoding support for multiply instructions. Some blanks left to ↵Jim Grosbach2008-11-034-41/+105
| | | | | | fill in, but the basics are there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor various TargetAsmInfo subclasses' TargetMachine members awayDan Gohman2008-11-0310-36/+32
| | | | | | | adding a TargetMachine member to the base TargetAsmInfo class instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58624 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace fixes. No functionality change.Bill Wendling2008-10-311-27/+27
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* Add comment.Evan Cheng2008-10-311-0/+2
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* Use better data structure for ConstPoolId2AddrMap.Evan Cheng2008-10-312-15/+20
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* Actually make debug output understandable.Evan Cheng2008-10-311-4/+4
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* x86_64 rip-relative and magic mode addressMon P Wang2008-10-311-4/+8
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* Forgot this in last commit.Evan Cheng2008-10-311-1/+1
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* Encode PICADD; some code clean up.Evan Cheng2008-10-311-76/+101
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* Revert r58489. It isn't correct for all cases.Bill Wendling2008-10-311-1/+2
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* Change x86 register allocation ordering to match that of gcc. Otherwise some ↵Evan Cheng2008-10-311-19/+19
| | | | | | tools get confused by prologue generated by llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58517 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't skip over all "terminator" instructions when determining where to put theBill Wendling2008-10-311-2/+1
| | | | | | | | | callee-saved restore code. It could skip over conditional jumps accidentally. Instead, just skip the "return" instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58489 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MOVSSmr instead of EXTRACTPSmr in the case of extractingDan Gohman2008-10-311-2/+6
| | | | | | | vector element 0 for a store, as it's smaller and faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58483 91177308-0d34-0410-b5e6-96231b3b80d8
* I think we got non-machine specific constpool entries covered.Evan Cheng2008-10-301-1/+2
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* Shift amounts should have type getShiftAmountTyDuncan Sands2008-10-301-9/+9
| | | | | | | | (i32 for PPC, not i8). Correct this, and some formatting while there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58451 91177308-0d34-0410-b5e6-96231b3b80d8
* Shift amounts should have the type given byDuncan Sands2008-10-301-5/+5
| | | | | | | getShiftAmountTy (i32 in the case of CellSPU). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58449 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM JIT should observe -relocation-model command line option.Evan Cheng2008-10-302-2/+6
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* Add initial support for vector widening. Logic is set to widen for X86.Mon P Wang2008-10-302-2/+50
| | | | | | | | One will only see an effect if legalizetype is not active. Will move support to LegalizeType soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58426 91177308-0d34-0410-b5e6-96231b3b80d8
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