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* Fix argument size for SHL, SHR, SAR, SHLD and SHRD families ofAlkis Evlogimenos2004-02-271-34/+34
| | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11923 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of ADD and SUB family of instructions. Also rearrangeAlkis Evlogimenos2004-02-271-22/+24
| | | | | | | them so that they are consistent with AND, XOR, etc... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11922 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}.Alkis Evlogimenos2004-02-275-223/+223
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11921 91177308-0d34-0410-b5e6-96231b3b80d8
* Add memory operand folding support for the SETcc family ofAlkis Evlogimenos2004-02-272-0/+25
| | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11907 91177308-0d34-0410-b5e6-96231b3b80d8
* Add memory operand folding support for SHLD and SHRD instructions.Alkis Evlogimenos2004-02-272-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11905 91177308-0d34-0410-b5e6-96231b3b80d8
* Add memory operand folding support for SHL, SHR and SAR, SHLD instructions.Alkis Evlogimenos2004-02-272-0/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11903 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SHL, SHR, SAR, SHLD and SHLR instructions to make themAlkis Evlogimenos2004-02-273-37/+40
| | | | | | | | consistent with the rest and also pepare for the addition of their memory operand variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11902 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes for PR258 and PR259.John Criswell2004-02-262-6/+6
| | | | | | | | | | Functions with linkonce linkage are declared with weak linkage. Global floating point constants used to represent unprintable values (such as NaN and infinity) are declared static so that they don't interfere with other CBE generated translation units. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11884 91177308-0d34-0410-b5e6-96231b3b80d8
* Uncomment assertions that register# != 0 on calls toAlkis Evlogimenos2004-02-262-8/+10
| | | | | | | | MRegisterInfo::is{Physical,Virtual}Register. Apply appropriate fixes to relevant files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11882 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a map instead of annotationsChris Lattner2004-02-261-23/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11875 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some warnings, some of which were spurious, and some of which were realChris Lattner2004-02-262-12/+12
| | | | | | | bugs. Thanks Brian! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11859 91177308-0d34-0410-b5e6-96231b3b80d8
* Instructions to call and return from functions.Misha Brukman2004-02-262-2/+50
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11858 91177308-0d34-0410-b5e6-96231b3b80d8
* Great sparc renaming fallout IV: Sparc --> SparcV9.Brian Gaeke2004-02-252-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11844 91177308-0d34-0410-b5e6-96231b3b80d8
* SparcV8 regs are really 32-bit, not 64! Thanks, Chris.Misha Brukman2004-02-252-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11835 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the tablegen descriptions for SparcV8.Misha Brukman2004-02-254-70/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11834 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the SparcV8 register definitions that were imported from PPC template.Misha Brukman2004-02-252-130/+50
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11833 91177308-0d34-0410-b5e6-96231b3b80d8
* SparcV8 has different types of instructions, but F1 is only used for CALL.Misha Brukman2004-02-254-0/+210
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11832 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix failures in 099.go due to the cfgsimplify pass creating switch instructionsChris Lattner2004-02-251-5/+6
| | | | | | | where there did not used to be any before git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11829 91177308-0d34-0410-b5e6-96231b3b80d8
* SparcV8 skeletonBrian Gaeke2004-02-2528-0/+1472
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11828 91177308-0d34-0410-b5e6-96231b3b80d8
* Great renaming part II: Sparc --> SparcV9 (also includes command-line ↵Brian Gaeke2004-02-252-2/+2
| | | | | | options and Makefiles) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11827 91177308-0d34-0410-b5e6-96231b3b80d8
* Great renaming: Sparc --> SparcV9Brian Gaeke2004-02-2534-375/+375
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the instruction selector how to transform 'array' GEP computations ↵Chris Lattner2004-02-252-48/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into X86 scaled indexes. This allows us to compile GEP's like this: int* %test([10 x { int, { int } }]* %X, int %Idx) { %Idx = cast int %Idx to long %X = getelementptr [10 x { int, { int } }]* %X, long 0, long %Idx, ubyte 1, ubyte 0 ret int* %X } Into a single address computation: test: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] lea %EAX, DWORD PTR [%EAX + 8*%ECX + 4] ret Before it generated: test: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] shl %ECX, 3 add %EAX, %ECX lea %EAX, DWORD PTR [%EAX + 4] ret This is useful for things like int/float/double arrays, as the indexing can be folded into the loads&stores, reducing register pressure and decreasing the pressure on the decode unit. With these changes, I expect our performance on 256.bzip2 and gzip to improve a lot. On bzip2 for example, we go from this: 10665 asm-printer - Number of machine instrs printed 40 ra-local - Number of loads/stores folded into instructions 1708 ra-local - Number of loads added 1532 ra-local - Number of stores added 1354 twoaddressinstruction - Number of instructions added 1354 twoaddressinstruction - Number of two-address instructions 2794 x86-peephole - Number of peephole optimization performed to this: 9873 asm-printer - Number of machine instrs printed 41 ra-local - Number of loads/stores folded into instructions 1710 ra-local - Number of loads added 1521 ra-local - Number of stores added 789 twoaddressinstruction - Number of instructions added 789 twoaddressinstruction - Number of two-address instructions 2142 x86-peephole - Number of peephole optimization performed ... and these types of instructions are often in tight loops. Linear scan is also helped, but not as much. It goes from: 8787 asm-printer - Number of machine instrs printed 2389 liveintervals - Number of identity moves eliminated after coalescing 2288 liveintervals - Number of interval joins performed 3522 liveintervals - Number of intervals after coalescing 5810 liveintervals - Number of original intervals 700 spiller - Number of loads added 487 spiller - Number of stores added 303 spiller - Number of register spills 1354 twoaddressinstruction - Number of instructions added 1354 twoaddressinstruction - Number of two-address instructions 363 x86-peephole - Number of peephole optimization performed to: 7982 asm-printer - Number of machine instrs printed 1759 liveintervals - Number of identity moves eliminated after coalescing 1658 liveintervals - Number of interval joins performed 3282 liveintervals - Number of intervals after coalescing 4940 liveintervals - Number of original intervals 635 spiller - Number of loads added 452 spiller - Number of stores added 288 spiller - Number of register spills 789 twoaddressinstruction - Number of instructions added 789 twoaddressinstruction - Number of two-address instructions 258 x86-peephole - Number of peephole optimization performed Though I'm not complaining about the drop in the number of intervals. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11820 91177308-0d34-0410-b5e6-96231b3b80d8
* * Make the previous patch more efficient by not allocating a temporary ↵Chris Lattner2004-02-252-112/+368
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MachineInstr to do analysis. *** FOLD getelementptr instructions into loads and stores when possible, making use of some of the crazy X86 addressing modes. For example, the following C++ program fragment: struct complex { double re, im; complex(double r, double i) : re(r), im(i) {} }; inline complex operator+(const complex& a, const complex& b) { return complex(a.re+b.re, a.im+b.im); } complex addone(const complex& arg) { return arg + complex(1,0); } Used to be compiled to: _Z6addoneRK7complex: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] *** mov %EDX, %ECX fld QWORD PTR [%EDX] fld1 faddp %ST(1) *** add %ECX, 8 fld QWORD PTR [%ECX] fldz faddp %ST(1) *** mov %ECX, %EAX fxch %ST(1) fstp QWORD PTR [%ECX] *** add %EAX, 8 fstp QWORD PTR [%EAX] ret Now it is compiled to: _Z6addoneRK7complex: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] fld QWORD PTR [%ECX] fld1 faddp %ST(1) fld QWORD PTR [%ECX + 8] fldz faddp %ST(1) fxch %ST(1) fstp QWORD PTR [%EAX] fstp QWORD PTR [%EAX + 8] ret Other programs should see similar improvements, across the board. Note that in addition to reducing instruction count, this also reduces register pressure a lot, always a good thing on X86. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11819 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a helper to create an addressing mode given all of the pieces.Chris Lattner2004-02-251-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11818 91177308-0d34-0410-b5e6-96231b3b80d8
* add an inefficient way of folding structure and constant array indexes togetherChris Lattner2004-02-252-44/+180
| | | | | | | | | | | | into a single LEA instruction. This should improve the code generated for things like X->A.B.C[12].D. The bigger benefit is still coming though. Note that this uses an LEA instruction instead of an add, giving the register allocator more freedom. We should probably never generate ADDri32's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11817 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement special case for storing an immediate into memory so that we don't ↵Chris Lattner2004-02-252-26/+58
| | | | | | | | | need an intermediate register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11816 91177308-0d34-0410-b5e6-96231b3b80d8
* FunctionLiveVarInfo.h moved: include/llvm/CodeGen -> lib/Target/Sparc/LiveVarBrian Gaeke2004-02-246-5/+116
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11804 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some unexpected fallout from the config.h changes. Because the CBE noChris Lattner2004-02-242-0/+2
| | | | | | | | longer was getting this #include, it always fell back on the less precise floating point initializer values, causing some testsuite failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11803 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor rewinding code for finding the first terminator of a basicAlkis Evlogimenos2004-02-232-12/+2
| | | | | | | | | | | | | block into MachineBasicBlock::getFirstTerminator(). This also fixes a bug in the implementation of the above in both RegAllocLocal and InstrSched, where instructions where added after the terminator if the basic block's only instruction was a terminator (it shouldn't matter for RegAllocLocal since this case never occurs in practice). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11748 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code a bit, don't go off the end of the block, now that the currentChris Lattner2004-02-232-22/+18
| | | | | | | block we are in might be empty git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11744 91177308-0d34-0410-b5e6-96231b3b80d8
* We were forgetting to add FP_REG_KILL instructions to basic blocks which willChris Lattner2004-02-232-30/+54
| | | | | | | eventually get an assignment due to elimination of PHIs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11743 91177308-0d34-0410-b5e6-96231b3b80d8
* Work around a gas bug. Print '-9223372036854775808' as unsigned.Chris Lattner2004-02-232-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11729 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement cast fp -> boolChris Lattner2004-02-232-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11728 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop passing iterators around by reference now that we have ilists!Chris Lattner2004-02-232-48/+108
| | | | | | | Implement cast Type::ULongTy -> double git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11726 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new cmove instructionChris Lattner2004-02-231-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11722 91177308-0d34-0410-b5e6-96231b3b80d8
* Only insert FP_REG_KILL instructions in MachineBasicBlocks that actuallyChris Lattner2004-02-222-96/+196
| | | | | | | | | | | | | | | | | use FP instructions. This reduces the number of instructions inserted in 176.gcc (for example) from 58074 to 101 (it doesn't use much FP, which is typical). This reduction speeds up the entire code generator. In the case of 176.gcc, llc went from taking 31.38s to 24.78s. The passes that sped up the most are the register allocator and the 2 live variable analysis passes, which sped up 2.3, 1.3, and 1.5s respectively. The asmprinter pass also sped up because it doesn't print the instructions in comments :) Note that this patch is likely to expose latent bugs in machine code passes, because now basicblock can be empty, where they were never empty before. I cleaned out regalloclocal, but who knows about linscan :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11717 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MOTy::UseType enum into MachineOperand. This eliminates theAlkis Evlogimenos2004-02-2210-67/+82
| | | | | | | | | | switch statements in the constructors and simplifies the implementation of the getUseType() member function. You will have to specify defs using MachineOperand::Def instead of MOTy::Def though (similarly for Use and UseAndDef). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11715 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce the number of pointless copies inserted due to constant pointer refs.Chris Lattner2004-02-222-12/+24
| | | | | | | Also, make an assertion actually fireable! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11713 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in previous checkout: leave the iterator at the first instructionChris Lattner2004-02-222-8/+6
| | | | | | | AFTER the GEP that was emitted. :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11712 91177308-0d34-0410-b5e6-96231b3b80d8
* Completely rewrite how getelementptr instructions are expanded. This has twoChris Lattner2004-02-222-84/+140
| | | | | | | | | | | | | | | (minor) benefits right now: 1. An extra dummy MOVrr32 is gone. This move would often be coallesced by both allocators anyway. 2. The code now uses the gep_type_iterator to walk the gep, which should future proof it a bit. It still assumes that array indexes are Longs though. These don't really justify rewriting the code. The big benefit will come later though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11710 91177308-0d34-0410-b5e6-96231b3b80d8
* When folding memory operands in machine instructions be careful toAlkis Evlogimenos2004-02-221-2/+4
| | | | | | | | leave register operands with the same use/def flags as the original instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11709 91177308-0d34-0410-b5e6-96231b3b80d8
* Wow this is out of date. When we have _real_ code generator documentation,Chris Lattner2004-02-221-42/+31
| | | | | | | this should be folded into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11705 91177308-0d34-0410-b5e6-96231b3b80d8
* The two address pass cannot handle two addr instructions where one incomingChris Lattner2004-02-222-18/+32
| | | | | | | | | value is a physreg and one is a virtreg. For this reason, disable copy folding entirely for physregs. Also, use the new isMoveInstr target hook which gives us folding of FP moves as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11700 91177308-0d34-0410-b5e6-96231b3b80d8
* It is totally unacceptable to print out (literally) millions of zeros whenChris Lattner2004-02-202-4/+26
| | | | | | | compiling 129.compress... so don't! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11649 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate operator[] is deprecated warningsChris Lattner2004-02-181-16/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11578 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix deprecated operator[] warningsChris Lattner2004-02-181-15/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11577 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix argument size for MOVSX and MOVZX instructions.Alkis Evlogimenos2004-02-181-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11576 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for GlobalAddress's for alkisChris Lattner2004-02-172-3/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11560 91177308-0d34-0410-b5e6-96231b3b80d8
* These store to memory too.Alkis Evlogimenos2004-02-171-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11558 91177308-0d34-0410-b5e6-96231b3b80d8
* These store to memory, not read from it.Chris Lattner2004-02-171-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11556 91177308-0d34-0410-b5e6-96231b3b80d8
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