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* Floating point regsBrian Gaeke2004-03-042-4/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12110 91177308-0d34-0410-b5e6-96231b3b80d8
* Simple copyConstantToReg support, SETHIi and ORriBrian Gaeke2004-03-046-16/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12107 91177308-0d34-0410-b5e6-96231b3b80d8
* Support add - note, still missing important copyConstantToRegister stuffBrian Gaeke2004-03-036-10/+614
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12106 91177308-0d34-0410-b5e6-96231b3b80d8
* SPECIFY a target data to initialize the CBE target with. Until now we haveChris Lattner2004-03-031-1/+1
| | | | | | | | | been using the default target data layout object to lower malloc instructions, causing us to allocate more memory than we needed! This could improve the performance of the CBE generated code substantially! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12088 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new constructorChris Lattner2004-03-031-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12087 91177308-0d34-0410-b5e6-96231b3b80d8
* Doxygenify some comments.Misha Brukman2004-03-014-18/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12064 91177308-0d34-0410-b5e6-96231b3b80d8
* Add this back, as its absence introduces assertions, and it seems to work nowChris Lattner2004-03-011-4/+1
| | | | | | | that Instructions are annotable again git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12045 91177308-0d34-0410-b5e6-96231b3b80d8
* fix bug in previous checkinTanya Lattner2004-03-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12044 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetCacheInfo has been removed; its only uses were to propagate a constantBrian Gaeke2004-03-019-49/+6
| | | | | | | | | | (16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in the interest of not breaking things any more than they already are, I'm going to leave the constant alone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12043 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding new Modulo Scheduling graph files.Tanya Lattner2004-03-013-0/+769
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12031 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing old graph files with new graph files that I wrote. Updated ↵Tanya Lattner2004-03-013-276/+682
| | | | | | ModuloScheduling pass, but still in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12030 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle passing constant integers to functions much more efficiently. InsteadChris Lattner2004-03-012-20/+46
| | | | | | | | | | | | | | | | | | | | | | | | of generating this code: mov %EAX, 4 mov DWORD PTR [%ESP], %EAX mov %AX, 123 movsx %EAX, %AX mov DWORD PTR [%ESP + 4], %EAX call Y we now generate: mov DWORD PTR [%ESP], 4 mov DWORD PTR [%ESP + 4], 123 call Y Which hurts the eyes less. :) Considering that register pressure around call sites is already high (with all of the callee clobber registers n stuff), this may help a lot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12028 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a minor code-quality issue. When passing 8 and 16-bit integer constantsChris Lattner2004-03-012-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to function calls, we would emit dead code, like this: int Y(int, short, double); int X() { Y(4, 123, 4); } --- Old X: sub %ESP, 20 mov %EAX, 4 mov DWORD PTR [%ESP], %EAX *** mov %AX, 123 mov %AX, 123 movsx %EAX, %AX mov DWORD PTR [%ESP + 4], %EAX fld QWORD PTR [.CPIX_0] fstp QWORD PTR [%ESP + 8] call Y mov %EAX, 0 # IMPLICIT_USE %EAX %ESP add %ESP, 20 ret Now we emit: X: sub %ESP, 20 mov %EAX, 4 mov DWORD PTR [%ESP], %EAX mov %AX, 123 movsx %EAX, %AX mov DWORD PTR [%ESP + 4], %EAX fld QWORD PTR [.CPIX_0] fstp QWORD PTR [%ESP + 8] call Y mov %EAX, 0 # IMPLICIT_USE %EAX %ESP add %ESP, 20 ret Next up, eliminate the mov AX and movsx entirely! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12026 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the private MachineInstrAnnot.h into a private directory.Chris Lattner2004-02-294-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12003 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not use explicit casts that hide the dependence on Instruction beingChris Lattner2004-02-291-8/+2
| | | | | | | annotable git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12000 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction name description.Alkis Evlogimenos2004-02-291-2/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11998 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct template for SHLD and SHRD instructions so that the memoryAlkis Evlogimenos2004-02-291-9/+9
| | | | | | | operand size is correctly specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11997 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve allocation order:Alkis Evlogimenos2004-02-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) For 8-bit registers try to use first the ones that are parts of the same register (AL then AH). This way we only alias 2 16/32-bit registers after allocating 4 8-bit variables. 2) Move EBX as the last register to allocate. This will cause less spills to happen since we will have 8-bit registers available up to register excaustion (assuming we use the allocation order). It would be nice if we could push all of the 8-bit aliased registers towards the end but we much prefer to keep callee saved register to the end to avoid saving them on entry and exit of the function. For example this gives a slight reduction of spills with linear scan on 164.gzip. Before: 11221 asm-printer - Number of machine instrs printed 975 spiller - Number of loads added 675 spiller - Number of stores added 398 spiller - Number of register spills After: 11182 asm-printer - Number of machine instrs printed 952 spiller - Number of loads added 652 spiller - Number of stores added 386 spiller - Number of register spills git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11996 91177308-0d34-0410-b5e6-96231b3b80d8
* A big X86 instruction rename. The instructions are renamed to makeAlkis Evlogimenos2004-02-2911-1021/+1021
| | | | | | | | | | | | | | | | | their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11995 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead member variables of SparcV9SchedInfo and TargetSchedInfoBrian Gaeke2004-02-291-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11994 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the X86-specific BMI functions, using BuildMI instead.Chris Lattner2004-02-292-374/+352
| | | | | | | Replace uses of addZImm with addImm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11992 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a miscompilation of 197.parser that occurs when you have single basicChris Lattner2004-02-292-16/+28
| | | | | | | block loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11990 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust to change in TII ctor argumentsChris Lattner2004-02-295-15/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11987 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the distinction between "real" and "unreal" instructionsChris Lattner2004-02-292-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11986 91177308-0d34-0410-b5e6-96231b3b80d8
* These two virtual methods are never called.Chris Lattner2004-02-298-105/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11984 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a TON of flags that noone cares aboutChris Lattner2004-02-291-362/+362
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11983 91177308-0d34-0410-b5e6-96231b3b80d8
* Noone calls these virtual methodsChris Lattner2004-02-291-26/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11982 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the only file in the system that uses this enum. eliminate it.Chris Lattner2004-02-291-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11981 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement initial prolog/epilog code insertion methods.Chris Lattner2004-02-294-12/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11979 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct template for ADC instruction with memory operands.Alkis Evlogimenos2004-02-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11974 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an instruction selector capable of selecting 'ret void'Chris Lattner2004-02-2910-14/+636
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* SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename themAlkis Evlogimenos2004-02-284-14/+14
| | | | | | | to denote this fact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11972 91177308-0d34-0410-b5e6-96231b3b80d8
* Floating point loads/stores act on memory operands. Rename them toAlkis Evlogimenos2004-02-288-71/+71
| | | | | | | denote this fact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11971 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename instruction templates to be easier to the human eye toAlkis Evlogimenos2004-02-281-254/+254
| | | | | | | | | | | | parse. The name is now I (operand size)*. For example: Im32 -> instruction with 32-bit memory operands. Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11970 91177308-0d34-0410-b5e6-96231b3b80d8
* Uncomment instructions that take both an immediate and a memoryAlkis Evlogimenos2004-02-283-21/+11
| | | | | | | operand but their sizes differ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11969 91177308-0d34-0410-b5e6-96231b3b80d8
* Each instruction now has both an ImmType and a MemType. This describesAlkis Evlogimenos2004-02-286-500/+542
| | | | | | | | | the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11967 91177308-0d34-0410-b5e6-96231b3b80d8
* Change this so that LLC actually tries to run the code generator, though it willChris Lattner2004-02-282-2/+2
| | | | | | | immediately abort due to lack of an instruction selector. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11963 91177308-0d34-0410-b5e6-96231b3b80d8
* SparcV8 now builds.Chris Lattner2004-02-281-1/+1
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* fine grainify namespacificationChris Lattner2004-02-281-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11959 91177308-0d34-0410-b5e6-96231b3b80d8
* Finegrainify namespacificationChris Lattner2004-02-282-12/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11958 91177308-0d34-0410-b5e6-96231b3b80d8
* Tab completion is our friend.Chris Lattner2004-02-2810-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11957 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up rulesChris Lattner2004-02-282-48/+30
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* Bring this directory into "it actually compiles" landChris Lattner2004-02-288-16/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11955 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix multiple inclusion problemChris Lattner2004-02-282-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11954 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not generate instructions with mismatched memory/immediate sizedAlkis Evlogimenos2004-02-284-36/+44
| | | | | | | operands. The X86 backend doesn't handle them properly right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11944 91177308-0d34-0410-b5e6-96231b3b80d8
* Further comment updates.Alkis Evlogimenos2004-02-281-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11933 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comments.Alkis Evlogimenos2004-02-281-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11932 91177308-0d34-0410-b5e6-96231b3b80d8
* My previous commit broke the jit. The shift instructions always takeAlkis Evlogimenos2004-02-281-16/+16
| | | | | | | | | | | | | | | | | an 8-bit immediate. So mark the shifts that take immediates as taking an 8-bit argument. The rest with the implicit use of CL are marked appropriately. A bug still exists: def SHLDmri32 : I2A8 <"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8 The immediate in the above instruction is 8-bit but the memory reference is 32-bit. The printer prints this as an 8-bit reference which confuses the assembler. Same with SHRDmri32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11931 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn off the SparcV9MachineCodeDestructionPass for now, because it's buggyBrian Gaeke2004-02-271-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11930 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct DestroyMachineFunction's getPassNameBrian Gaeke2004-02-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11929 91177308-0d34-0410-b5e6-96231b3b80d8
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