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* Update the CMake files.Bill Wendling2012-06-292-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159417 91177308-0d34-0410-b5e6-96231b3b80d8
* The DIBuilder class is just a wrapper around debug info creationBill Wendling2012-06-296-7/+7
| | | | | | | | (a.k.a. MDNodes). The module doesn't belong in Analysis. Move it to the VMCore instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159414 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-295-64/+49
| | | | | | This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
* In the initial exec mode we always do a load to find the address of a variable.Rafael Espindola2012-06-291-4/+4
| | | | | | | | | Before this patch in pic 32 bit code we would add the global base register and not load from that address. This is a really old bug, but before the introduction of the tls attributes we would never select initial exec for pic code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159409 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: avoid scheduling instructions that can't be dispatched.Andrew Trick2012-06-291-6/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159408 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: count micro-ops toward the issue limit.Andrew Trick2012-06-291-10/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159407 91177308-0d34-0410-b5e6-96231b3b80d8
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-295-49/+64
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-294-23/+60
| | | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
* If the step value is a constant zero, the loop isn't going to terminate. FixesNick Lewycky2012-06-281-1/+1
| | | | | | | the assert reported in PR13228! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159393 91177308-0d34-0410-b5e6-96231b3b80d8
* make the verifier accept @llvm.donothing as the only intrinsic that can be ↵Nuno Lopes2012-06-281-2/+4
| | | | | | | | invoked While at it, merge 2 tests and FileCheckize them git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159388 91177308-0d34-0410-b5e6-96231b3b80d8
* make simplifyCFG erase invokes to readonly/readnone functionsNuno Lopes2012-06-281-6/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159385 91177308-0d34-0410-b5e6-96231b3b80d8
* make instcombine produce calls to llvm.donothing instead of a random intrinsicNuno Lopes2012-06-281-7/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159384 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new @llvm.donothing intrinsic that, well, does nothing, and teach ↵Nuno Lopes2012-06-281-1/+8
| | | | | | CodeGen to ignore calls to it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159383 91177308-0d34-0410-b5e6-96231b3b80d8
* 'Promote' vector [su]int_to_fp should widen elements.Jim Grosbach2012-06-281-3/+54
| | | | | | | | | | | Teach vector legalization how to honor Promote for int to float conversions. The code checking whether to promote the operation knew to look at the operand, but the actual promotion code didn't. This fixes that. The operand is promoted up via [zs]ext. rdar://11762659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159378 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed the formatting sequence of a curly brace to Jack Carter2012-06-281-2/+2
| | | | | | | the comment per code review feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159376 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove layering violation #include.Bill Wendling2012-06-281-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159372 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable automatic GCC<->LLVM intrinsic translation for mips.Benjamin Kramer2012-06-281-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159367 91177308-0d34-0410-b5e6-96231b3b80d8
* MemoryBuiltins:Nuno Lopes2012-06-281-14/+37
| | | | | | | | - recognize C++ new(std::nothrow) friends - ignore ExtractElement and ExtractValue instructions in size/offset analysis (all easy cases are probably folded away before we get here) - also recognize realloc as noalias git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159356 91177308-0d34-0410-b5e6-96231b3b80d8
* make LazyValueInfo analyze the default case of switch statements (we know ↵Nuno Lopes2012-06-281-16/+15
| | | | | | that in the default branch the value cannot be any of the switch cases) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159353 91177308-0d34-0410-b5e6-96231b3b80d8
* add ConstantRange::difference (to perform set difference/relative complement)Nuno Lopes2012-06-281-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159352 91177308-0d34-0410-b5e6-96231b3b80d8
* Devirtualize DIScope and subclasses.Benjamin Kramer2012-06-281-26/+0
| | | | | | Nothing in here makes use of the virtuality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159349 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] set a hard limit on the number of instructions instrumented pear each ↵Kostya Serebryany2012-06-281-0/+12
| | | | | | BB. This is (hopefully temporary) workaround for PR13225 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159344 91177308-0d34-0410-b5e6-96231b3b80d8
* Precompute SCEV pointer analysis prior to instruction fusion in BBVectorize.Hal Finkel2012-06-281-10/+51
| | | | | | | | | | | | | When both a load/store and its address computation are being vectorized, it can happen that the address-computation vectorization destroys SCEV's ability to analyize the relative pointer offsets. As a result (like with the aliasing analysis info), we need to precompute the necessary information prior to instruction fusing. This was found during stress testing (running through the test suite with a very low required chain length); unfortunately, I don't have a small test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159332 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a useless check in BBVectorize.Hal Finkel2012-06-281-5/+0
| | | | | | | A shuffle mask will always be a constant, but I did not realize that when I originally wrote the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159331 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow BBVectorize to form non-2^n-length vectors.Hal Finkel2012-06-281-132/+532
| | | | | | | | | | | | | | | | | | | | The original algorithm only used recursive pair fusion of equal-length types. This is now extended to allow pairing of any types that share the same underlying scalar type. Because we would still generally prefer the 2^n-length types, those are formed first. Then a second set of iterations form the non-2^n-length types. Also, a call to SimplifyInstructionsInBlock has been added after each pairing iteration. This takes care of DCE (and a few other things) that make the following iterations execute somewhat faster. For the same reason, some of the simple shuffle-combination cases are now handled internally. There is some additional refactoring work to be done, but I've had many requests for this feature, so additional refactoring will come soon in future commits (as will additional test cases). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159330 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor operation equivalence checking in BBVectorize by extending ↵Hal Finkel2012-06-282-28/+18
| | | | | | | | | | | Instruction::isSameOperationAs. Maintaining this kind of checking in different places is dangerous, extending Instruction::isSameOperationAs consolidates this logic into one place. Here I've added an optional flags parameter and two flags that are important for vectorization: CompareIgnoringAlignment and CompareUsingScalarTypes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159329 91177308-0d34-0410-b5e6-96231b3b80d8
* Only print out the tag if it's there.Bill Wendling2012-06-281-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159328 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't output an empty string.Bill Wendling2012-06-281-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159327 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips specific inline asm operand modifier 'z' has theJack Carter2012-06-281-1/+13
| | | | | | | | | following description in the gnu sources: Print $0 if operand is zero otherwise print the op normally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159324 91177308-0d34-0410-b5e6-96231b3b80d8
* make LVI::getEdgeValue() always intersect the constraints of the edge with ↵Nuno Lopes2012-06-281-36/+53
| | | | | | the range of the block. Previously it was only performing the intersection for a few cases, thus losing precision git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159320 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a off-by-one bug in intersectWith(), and add a bunch of testsNuno Lopes2012-06-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159319 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the interface through DIDescriptor to get the tag/version for a debug infoBill Wendling2012-06-281-9/+11
| | | | | | | MDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159317 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix cmake failure from moving files around.Bill Wendling2012-06-282-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159314 91177308-0d34-0410-b5e6-96231b3b80d8
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-2838-103/+101
| | | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159312 91177308-0d34-0410-b5e6-96231b3b80d8
* This allows hello world to be compiled for Mips 64 direct object.Jack Carter2012-06-271-0/+1
| | | | | | | | | | | | It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159302 91177308-0d34-0410-b5e6-96231b3b80d8
* This allows hello world to be compiled for Mips 64 direct object.Jack Carter2012-06-274-3/+54
| | | | | | | | | | | | It takes advantage of r159299 which introduces relocation support for N64. elf-dump needed to be upgraded to support N64 relocations as well. This passes make check. Jack git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159301 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Chad Rosier2012-06-271-34/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159300 91177308-0d34-0410-b5e6-96231b3b80d8
* The ELF relocation record format is different for N64 Jack Carter2012-06-273-12/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | which many Mips 64 ABIs use than for O64 which many if not all other target ABIs use. Most architectures have the following 64 bit relocation record format: typedef struct { Elf64_Addr r_offset; /* Address of reference */ Elf64_Xword r_info; /* Symbol index and type of relocation */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset; Elf64_Xword r_info; Elf64_Sxword r_addend; } Elf64_Rela; Whereas N64 has the following format: typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ } Elf64_Rel; typedef struct { Elf64_Addr r_offset;/* Address of reference */ Elf64_Word r_sym; /* Symbol index */ Elf64_Byte r_ssym; /* Special symbol */ Elf64_Byte r_type3; /* Relocation type */ Elf64_Byte r_type2; /* Relocation type */ Elf64_Byte r_type; /* Relocation type */ Elf64_Sxword r_addend; } Elf64_Rela; The structure is the same size, but the r_info data element is now 5 separate elements. Besides the content aspects, endian byte reordering will be different for the area with each element being endianized separately. I treat this as generic and continue to pass r_type as an integer masking and unmasking the byte sized N64 values for N64 mode. I've implemented this and it causes no affect on other current targets. This passes make check. Jack git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159299 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r159136 due to PR13124.Matt Beaumont-Gay2012-06-271-11/+0
| | | | | | | | | | | Original commit message: If a constant or a function has linkonce_odr linkage and unnamed_addr, mark it hidden. Being linkonce_odr guarantees that it is available in every dso that needs it. Being a constant/function with unnamed_addr guarantees that the copies don't have to be merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159272 91177308-0d34-0410-b5e6-96231b3b80d8
* Some reassociate optimizations create new instructions, which they insert justDuncan Sands2012-06-271-11/+7
| | | | | | | | | | | | before the expression root. Any existing operators that are changed to use one of them needs to be moved between it and the expression root, and recursively for the operators using that one. When I rewrote RewriteExprTree I accidentally inverted the logic, resulting in the compacting going down from operators to operands rather than up from operands to the operators using them, oops. Fix this, resolving PR12963. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159265 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach assembler to handle capitalised operation values for DSB instructionsRichard Barton2012-06-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159259 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent ARM Assembler crashing on unrecognised assembly format for DSB ↵Richard Barton2012-06-271-1/+2
| | | | | | instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159257 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka2012-06-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159243 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2012-06-272-3/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159240 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce indentation in function. Rearrange some methods. No functionality change.Bill Wendling2012-06-261-223/+222
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159239 91177308-0d34-0410-b5e6-96231b3b80d8
* Revamp how debugging information is emitted for debug info objects.Bill Wendling2012-06-261-134/+84
| | | | | | | | | | It's not necessary for each DI class to have its own copy of `print' and `dump'. Instead, just give DIDescriptor those methods and have it call the appropriate debugging printing routine based on the type of the debug information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159237 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing check to avoid dereference null. No sensible test case ↵Evan Cheng2012-06-261-0/+2
| | | | | | possible. Sorry. rdar://11745134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159236 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a instcombine transform that (no longer?) makes sense:Evan Cheng2012-06-261-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | // C - zext(bool) -> bool ? C - 1 : C if (ZExtInst *ZI = dyn_cast<ZExtInst>(Op1)) if (ZI->getSrcTy()->isIntegerTy(1)) return SelectInst::Create(ZI->getOperand(0), SubOne(C), C); This ends up forming sext i1 instructions that codegen to terrible code. e.g. int blah(_Bool x, _Bool y) { return (x - y) + 1; } => movzbl %dil, %eax movzbl %sil, %ecx shll $31, %ecx sarl $31, %ecx leal 1(%rax,%rcx), %eax ret Without the rule, llvm now generates: movzbl %sil, %ecx movzbl %dil, %eax incl %eax subl %ecx, %eax ret It also helps with ARM (and pretty much any target that doesn't have a sext i1 :-). The transformation was done as part of Eli's r75531. He has given the ok to remove it. rdar://11748024 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159230 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement getHostCPUName for ARM/linux. This will be used to implement ↵Benjamin Kramer2012-06-261-0/+55
| | | | | | | | | | -march=native in clang. The cpuid registers are only available in privileged mode so we don't have an OS-independent way of implementing this. ARM doesn't provide a list of processor IDs so the list is somewhat incomplete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159228 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-267-4/+132
| | | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
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