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* Make GVN look through extractvalues for recognised intrinsics. GVN can then ↵Lang Hames2011-07-081-7/+54
| | | | | | CSE ops that match values produced by the intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134677 91177308-0d34-0410-b5e6-96231b3b80d8
* Raise assertion when MachineOperand has unexpected target flag.Akira Hatanaka2011-07-081-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134671 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure variable Kind is assigned a value to suppress warning.Akira Hatanaka2011-07-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134668 91177308-0d34-0410-b5e6-96231b3b80d8
* Let the inline asm 'q' constraint match float, and on 64-bit double too.Nick Lewycky2011-07-081-3/+3
| | | | | | | Fixes PR9602! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8
* Go ahead and emit the barrier on x86-64 even without sse2. TheEric Christopher2011-07-081-3/+4
| | | | | | | | | processor supports it just fine. Fixes PR9675 and rdar://9740801 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower MachineInstr to MC Inst and print to .s files. Akira Hatanaka2011-07-0713-107/+290
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle fpcr register.Eric Christopher2011-07-071-1/+2
| | | | | | Part of PR10299 and rdar://9740322 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134653 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the X86 'l' constraint.Eric Christopher2011-07-071-0/+1
| | | | | | Fixes PR10149 and rdar://9738585 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a FIXME. All of the standard ones are in the list.Eric Christopher2011-07-071-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134647 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary newline.Akira Hatanaka2011-07-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134645 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DEBUG message.Devang Patel2011-07-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134643 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Mode64Bit feature and sink it down to MC layer.Evan Cheng2011-07-076-92/+177
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
* Move a function out-of-line.Bill Wendling2011-07-071-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134640 91177308-0d34-0410-b5e6-96231b3b80d8
* Rather than having printMemOperand change the way memory operands are printedAkira Hatanaka2011-07-073-16/+21
| | | | | | | | based on a modifier, split it into two functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134637 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds a flag in MCAsmInfo that indicates whether dwarf registerAkira Hatanaka2011-07-072-1/+2
| | | | | | | | | | | | numbers should be printed instead of symbolic register names in MCAsmStreamer::EmitRegisterName. This is necessary because some versions of GNU assembler won't accept code in which symbolic register names are used in cfi directives. There is no change in behavior unless the flag is explicitly set to true by a backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134635 91177308-0d34-0410-b5e6-96231b3b80d8
* Define class MipsMCInstLower.Akira Hatanaka2011-07-073-0/+161
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134633 91177308-0d34-0410-b5e6-96231b3b80d8
* Change visibility of MipsAsmPrinter.Akira Hatanaka2011-07-072-60/+87
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134630 91177308-0d34-0410-b5e6-96231b3b80d8
* Define class MipsMCSymbolRefExpr.Akira Hatanaka2011-07-073-0/+126
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134629 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify MipsRegisterInfo::eliminateFrameIndex.Akira Hatanaka2011-07-071-33/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134628 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite comment in English.Evan Cheng2011-07-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134627 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename attribute 'thumb' to a more descriptive 'thumb-mode'.Evan Cheng2011-07-074-9/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse order of operands of address operand mem so that the base operand comesAkira Hatanaka2011-07-077-50/+50
| | | | | | | | | | | before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing return statement.Akira Hatanaka2011-07-071-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134622 91177308-0d34-0410-b5e6-96231b3b80d8
* If known DebugLocs do not match then two DBG_VALUE machine instructions are ↵Devang Patel2011-07-071-0/+5
| | | | | | | | | | | | not identical. For example, DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ] DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ] These two MIs represent identical value, 3.31..., for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134620 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize mipseb as alias for mips for symmetry with mipsel.Joerg Sonnenberger2011-07-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134617 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CMake library dependenciesOscar Fuentes2011-07-071-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134616 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CMake buildDouglas Gregor2011-07-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134614 91177308-0d34-0410-b5e6-96231b3b80d8
* The VMLA instruction and its friends are not actually fused; they're plain oldCameron Zwarich2011-07-072-2/+2
| | | | | | multiply-accumulate instructions with separate rounding steps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134609 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink feature IsThumb into MC layer.Evan Cheng2011-07-074-15/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-0730-76/+118
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
* type can be nullChris Lattner2011-07-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134601 91177308-0d34-0410-b5e6-96231b3b80d8
* use a more efficient check for 'is metadata'Chris Lattner2011-07-071-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134599 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ArrayRef instead of a std::vector&.Bill Wendling2011-07-072-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134595 91177308-0d34-0410-b5e6-96231b3b80d8
* Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. TheLang Hames2011-07-072-16/+36
| | | | | | | | | | | | | | | | | | hasPredecessorHelper function allows predecessors to be cached to speed up repeated invocations. This fixes PR10186. X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X) Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with empty Visited and Worklist sets (i.e. no caching over invocations). Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited and Worklist to speed up repeated calls. The Visited set is searched for X before going to the worklist to further search the DAG if necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134592 91177308-0d34-0410-b5e6-96231b3b80d8
* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-074-113/+124
| | | | | | them down to MC layer. Also fix tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a target hook to encode the compact unwind information.Bill Wendling2011-07-074-9/+114
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134577 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DEBUG messages.Devang Patel2011-07-071-2/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134572 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor ARM triple parsing out of ARMSubtarget. Another step towards making ↵Evan Cheng2011-07-077-91/+84
| | | | | | ARM subtarget info available to MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8
* Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion.Devang Patel2011-07-071-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134568 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the "expect" intrinsic lowering.Jakub Staszak2011-07-061-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134566 91177308-0d34-0410-b5e6-96231b3b80d8
* When tail-merging multiple blocks, make sure to correctly update the live-in ↵Eli Friedman2011-07-062-10/+23
| | | | | | | | | | | | list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces. <rdar://problem/9716278> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134565 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code.Devang Patel2011-07-061-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134561 91177308-0d34-0410-b5e6-96231b3b80d8
* Typo.Devang Patel2011-07-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134559 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the #includes.Bill Wendling2011-07-061-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134557 91177308-0d34-0410-b5e6-96231b3b80d8
* Grammar and 80-col.Eric Christopher2011-07-061-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134555 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to ↵Devang Patel2011-07-061-11/+58
| | | | | | one alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134549 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM MC registry routines.Evan Cheng2011-07-067-12/+129
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename files for consistency.Evan Cheng2011-07-067-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134546 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark ARM pseudo-instructions as isPseudo.Jim Grosbach2011-07-061-5/+3
| | | | | | | | | | | | This allows us to remove the (bogus and unneeded) encoding information from the pseudo-instruction class definitions. All of the pseudos that haven't been converted yet and still need encoding information instance from the normal instruction classes and explicitly set isCodeGenOnly, and so are distinct from this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134540 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify. Consolidate dbg.declare handling in AllocaPromoter.Devang Patel2011-07-063-25/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134538 91177308-0d34-0410-b5e6-96231b3b80d8
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