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* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-305-100/+74
| | | | | | | | | | | | Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix rematerialization into physical registers.Tim Northover2013-05-301-2/+3
| | | | | | | | | | | | | | | | | r182872 introduced a bug in how the register-coalescer's rematerialization handled defining a physical register. It relied on the output of the coalescer's setRegisters method to determine whether the replacement instruction needed an implicit-def. However, this value isn't necessarily the same as the CopyMI's actual destination register which is what the rest of the basic-block expects us to be defining. The commit changes the rematerializer to use the actual register attached to CopyMI in its decision. This will be tested soon by an X86 patch which moves everything to using MOV32r0 instead of other sizes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182925 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix case where a sext load of an i1 type may produce anJustin Holewinski2013-05-301-2/+4
| | | | | | ld.u1 instead of an ld.u8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182924 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change zext moves to use sub-register infrastructure.Tim Northover2013-05-305-71/+74
| | | | | | | | | | | | 32-bit writes on amd64 zero out the high bits of the corresponding 64-bit register. LLVM makes use of this for zero-extension, but until now relied on custom MCLowering and other code to fixup instructions. Now we have proper handling of sub-registers, this can be done by creating SUBREG_TO_REG instructions at selection-time. Should be no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182921 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-302-0/+11
| | | | | | | | The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182920 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r182909.Evgeniy Stepanov2013-05-302-246/+0
| | | | | | | PR/16177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182919 91177308-0d34-0410-b5e6-96231b3b80d8
* Swizzle vector inputs if it helps us eliminate shuffles.Nick Lewycky2013-05-302-0/+246
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182909 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how we iterate over relocations on ELF.Rafael Espindola2013-05-304-16/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | For COFF and MachO, sections semantically have relocations that apply to them. That is not the case on ELF. In relocatable objects (.o), a section with relocations in ELF has offsets to another section where the relocations should be applied. In dynamic objects and executables, relocations don't have an offset, they have a virtual address. The section sh_info may or may not point to another section, but that is not actually used for resolving the relocations. This patch exposes that in the ObjectFile API. It has the following advantages: * Most (all?) clients can handle this more efficiently. They will normally walk all relocations, so doing an effort to iterate in a particular order doesn't save time. * llvm-readobj now prints relocations in the same way the native readelf does. * probably most important, relocations that don't point to any section are now visible. This is the case of relocations in the rela.dyn section. See the updated relocation-executable.test for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename variable to be more descriptive.Eric Christopher2013-05-301-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182903 91177308-0d34-0410-b5e6-96231b3b80d8
* Formatting.Eric Christopher2013-05-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182902 91177308-0d34-0410-b5e6-96231b3b80d8
* Reformat comments here.Eric Christopher2013-05-301-26/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182901 91177308-0d34-0410-b5e6-96231b3b80d8
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-2913-36/+53
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix Defs/Uses for insts that imp-def/imp-use both an A-register and EFLAGS.Ahmed Bougacha2013-05-291-66/+74
| | | | | | | | | | | | | | | This corrects a problem where x86 instructions that implicitly define/use both an A-register (RAX, EAX, ..) and EFLAGS were declared as only defining/using EFLAGS, because the outer "let Defs/Uses = [EFLAGS]" in the various multiclasses overrides the "let Defs/Uses = [areg]" in BinOpAI. The instructions deriving from BinOpAI were moved out of the "let Defs", and a BinOpAI_FF class was created, for instructions that implicitly define and use EFLAGS and the A-register (SBC, ADC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182883 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assume the registers will be enumerated sequentially.Chad Rosier2013-05-291-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182879 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable FastISel on ARM for Linux and NaClJF Bastien2013-05-291-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182877 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't reach into the middle of TargetMachine and cache one of its ivars.Bill Wendling2013-05-293-3/+4
| | | | | | | Not only does this break encapsulation, it's gross. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182876 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ReMaterialization to be more cunning about subregistersTim Northover2013-05-291-18/+65
| | | | | | | | | | | | | | | | This allows rematerialization during register coalescing to handle more cases involving operations like SUBREG_TO_REG which might need to be rematerialized using sub-register indices. For example, code like: v1(GPR64):sub_32 = MOVZ something v2(GPR64) = COPY v1(GPR64) should be convertable to: v2(GPR64):sub_32 = MOVZ something but previously we just gave up in places like this git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182872 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify logic by using the appropriate functions.Adrian Prantl2013-05-291-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182869 91177308-0d34-0410-b5e6-96231b3b80d8
* LTO+Debug Info: revert r182791.Manman Ren2013-05-293-54/+13
| | | | | | | | | | | | | Since the testing case uses ref_addr, which requires version 3+ to work, we will solve the dwarf version issue first. This patch also causes failures in one of the bots. I will update the patch accordingly in my next attempt. rdar://13926659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182867 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy some register classes for ARM and ThumbJF Bastien2013-05-292-3/+3
| | | | | | | | | | | | | | | | | | Tidy up three places where the register class for ARM and Thumb wasn't restrictive enough: - No PC dest for reg-reg add/orr/sub. - No PC dest for shifts. - No PC or SP for Thumb2 reg-imm add. I encountered this while combining FastISel with -verify-machineinstrs. These instructions defined registers whose classes weren't restrictive enough, and the uses failed verification. They're also undefined in the ISA, or would produce code that FastISel wouldn't want. This doesn't fix the register class narrowing issue (where uses should restrict definitions), and isn't thorough, but it's a small step in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182863 91177308-0d34-0410-b5e6-96231b3b80d8
* SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. ↵NAKAMURA Takumi2013-05-291-1/+1
| | | | | | [-Wunused-function] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182850 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-297-11/+59
| | | | | | | This patch adds support for the CIJ and CGIJ instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182846 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporary fix to get rid of gcc warning.Patrik Hagglund2013-05-291-1/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182832 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for leaf functions in sparc backend. Venkatraman Govindaraju2013-05-296-28/+123
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182822 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize.cpp: Fix abuse of StringRef on Twine. Twine captures the ↵NAKAMURA Takumi2013-05-291-2/+1
| | | | | | pointer of StringRef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182820 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.NAKAMURA Takumi2013-05-291-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182819 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Improve set register alias handlingJack Carter2013-05-281-5/+28
| | | | | | | | | | | | | | | | | This patch solves the problem of numeric register values not being accepted: ../set_alias.s:1:11: error: expected valid expression after comma .set r4,$4 ^ The parsing of .set directive is changed and handling of symbols in code as well to enable this feature. The test example is added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182807 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: clarify -help messageTim Northover2013-05-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182804 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for llvm.vectorizer metadataPaul Redmond2013-05-282-26/+196
| | | | | | | | | | | | | | | | | | | | - llvm.loop.parallel metadata has been renamed to llvm.loop to be more generic by making the root of additional loop metadata. - Loop::isAnnotatedParallel now looks for llvm.loop and associated llvm.mem.parallel_loop_access - document llvm.loop and update llvm.mem.parallel_loop_access - add support for llvm.vectorizer.width and llvm.vectorizer.unroll - document llvm.vectorizer.* metadata - add utility class LoopVectorizerHints for getting/setting loop metadata - use llvm.vectorizer.width=1 to indicate already vectorized instead of already_vectorized - update existing tests that used llvm.loop.parallel and llvm.vectorizer.already_vectorized Reviewed by: Nadav Rotem git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182802 91177308-0d34-0410-b5e6-96231b3b80d8
* [APInt] Implement tcDecrement as a counterpart to tcIncrement. This is for ↵Michael Gottesman2013-05-281-0/+14
| | | | | | | | use in APFloat IEEE-754R 2008 nextUp/nextDown function. rdar://13852078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182801 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: use pristine object file while processing relocationsTim Northover2013-05-281-15/+23
| | | | | | | | | | | | | | Previously we would read-modify-write the target bits when processing relocations for the MCJIT. This had the problem that when relocations were processed multiple times for the same object file (as they can be), the result is not idempotent and the values became corrupted. The solution to this is to take any bits used in the destination from the pristine object file as LLVM emitted it. This should fix PR16013 and remote MCJIT on ARM ELF targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182800 91177308-0d34-0410-b5e6-96231b3b80d8
* LTO+Debug Info: correctly emit inlined_subroutine when the inlined callee isManman Ren2013-05-283-13/+54
| | | | | | | | | | | | | from a different CU. We used to print out an error message and fail to generate inlined_subroutine. If we use ref_addr in the generated DWARF, the DWARF version should be 3 or above. rdar://13926659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182791 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Typo fix.Jyotsna Verma2013-05-281-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182790 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code. No functionality change.Benjamin Kramer2013-05-281-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182779 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove double semicolons.Benjamin Kramer2013-05-283-62/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182778 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend RemapInstruction and friends to take an optional new parameter, a ↵James Molloy2013-05-283-62/+99
| | | | | | | | ValueMaterializer. Extend LinkModules to pass a ValueMaterializer to RemapInstruction and friends to lazily create Functions for lazily linked globals. This is a big win when linking small modules with large (mostly unused) library modules. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182776 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Fix argument shadow alignment.Evgeniy Stepanov2013-05-281-4/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182771 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-287-28/+237
| | | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Tweak SystemZInstrInfo::isBranch() interfaceRichard Sandiford2013-05-283-33/+34
| | | | | | | | This is needed for the upcoming compare-and-branch patch. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182762 91177308-0d34-0410-b5e6-96231b3b80d8
* Make BasicAliasAnalysis recognize the fact a noalias argument cannot alias ↵Michael Kuperstein2013-05-282-4/+24
| | | | | | another argument, even if the other argument is not itself marked noalias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182755 91177308-0d34-0410-b5e6-96231b3b80d8
* Make it explicit that GlobalAlias are ok in llvm.used.Rafael Espindola2013-05-271-5/+4
| | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182747 91177308-0d34-0410-b5e6-96231b3b80d8
* Make helper functions static.Rafael Espindola2013-05-274-113/+65
| | | | | | And remove header and cpp file that are empty after that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182746 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert sqrt functions into sqrt instructions when -ffast-math is in effect.Preston Gurd2013-05-272-0/+6
| | | | | | | | | | | | | | | | When -ffast-math is in effect (on Linux, at least), clang defines __FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the preprocessor to include <bits/math-finite.h>, which renames the sqrt functions. For instance, "sqrt" is renamed as "__sqrt_finite". This patch adds the 3 new names in such a way that they will be treated as equivalent to their respective original names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182739 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Add a isConsecutiveLS utility functionHal Finkel2013-05-271-2/+42
| | | | | | | | | | | | | isConsecutiveLS is a slightly more general form of SelectionDAG::isConsecutiveLoad. Aside from also handling stores, it also does not assume equality of the chain operands is necessary. In the case of the PPC backend, this chain condition is checked in a more general way by the surrounding code. Mostly, this part of the refactoring in preparation for supporting optimized unaligned stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182723 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefer to duplicate PPC Altivec loads when expanding unaligned loadsHal Finkel2013-05-261-3/+79
| | | | | | | | | | | | | | | | | | | When expanding unaligned Altivec loads, we use the decremented offset trick to prevent page faults. Unfortunately, if we have a sequence of consecutive unaligned loads, this leads to suboptimal code generation because the 'extra' load from the first unaligned load can be combined with the base load from the second (but only if the decremented offset trick is not used for the first). Search up and down the chain, through loads and token factors, looking for consecutive loads, and if one is found, don't use the offset reduction trick. These duplicate loads are later combined to yield the desired sequence (in the future, we might want a more-powerful chain search, but that will require some changes to allow the combiner routines to access the AA object). This should complete the initial implementation of the optimized unaligned Altivec load expansion. There is some refactoring that should be done, but that will happen when the unaligned store expansion is added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182719 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16143: Insert DEBUG_VALUE before terminator.Andrew Trick2013-05-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182717 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for DWARF line number table entries for values in the instructionCameron Zwarich2013-05-251-0/+2
| | | | | | stream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182712 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Combine duplicate (offset) lvsl Altivec intrinsicsHal Finkel2013-05-251-1/+28
| | | | | | | | | The lvsl permutation control instruction is a function only of the alignment of the pointer operand (relative to the 16-byte natural alignment of Altivec vectors). As a result, multiple lvsl intrinsics where the operands differ by a multiple of 16 can be combined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182708 91177308-0d34-0410-b5e6-96231b3b80d8
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-2510-165/+17
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-2570-2026/+2028
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
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