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* In instcombine's debug output, avoid printing ADD for instructions that areJeffrey Yasskin2009-10-081-3/+5
| | | | | | | | already on the worklist, and print Visited when an instruction is about to be visited. Net, on one input, this reduced the output size by at least 9x. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83510 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-073-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-073-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-073-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting thumb1 scavenging default due to test failure while I figure out ↵Jim Grosbach2009-10-074-15/+74
| | | | | | what's up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83501 91177308-0d34-0410-b5e6-96231b3b80d8
* second half of lazy liveness removal.Chris Lattner2009-10-071-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83500 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of x86 'R' constraint.Dale Johannesen2009-10-071-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83499 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-072-10/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83496 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-072-64/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83494 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract subprogram and compile unit information from the debug info attached ↵Devang Patel2009-10-071-0/+29
| | | | | | to an instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83491 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some instruction encoding bits for NEON load/store instructions.Bob Wilson2009-10-072-140/+165
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83490 91177308-0d34-0410-b5e6-96231b3b80d8
* 80-column and whitespace fixes.Eric Christopher2009-10-071-135/+156
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83489 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed MCSectionMachO::ParseSectionSpecifier to allow an attribute of "none" soKevin Enderby2009-10-071-4/+6
| | | | | | | | that a symbol stub section with no attributes can be parsed as in: .section __TEXT,__picsymbolstub4,symbol_stubs,none,16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83488 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vst4 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-9/+94
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vst3 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-9/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
* grammarJim Grosbach2009-10-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83483 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vst2 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-7/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
* add initializers for clarity. Add missing assignment of PrevLastUseOp.Jim Grosbach2009-10-071-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83481 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove LazyLiveness from the tree. It doesn't work right now, and I'm not ↵Owen Anderson2009-10-071-168/+0
| | | | | | | | | going to have the time to finish it any time soon. If someone's interested it, they can resurrect it from SVN history. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83480 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vld4 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-7/+83
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
* Add another bit of the ARM target assembler to llvm-mc to parse registersKevin Enderby2009-10-071-3/+17
| | | | | | | | | with writeback, things like "sp!", etc. Also added some more stuff to the temporarily hacked methods ARMAsmParser::MatchRegisterName and ARMAsmParser::MatchInstruction to allow more parser testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83477 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, andDan Gohman2009-10-071-23/+28
| | | | | | | teach it how to recognize invariant physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83476 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TargetInstrInfo::isInvariantLoad and its target-specificDan Gohman2009-10-0710-97/+48
| | | | | | | | | | implementations with a new MachineInstr::isInvariantLoad, which uses MachineMemOperands and is target-independent. This brings MachineLICM and other functionality to targets which previously lacked an isInvariantLoad implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83475 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few simple MachineVerifier checks for MachineMemOperands.Dan Gohman2009-10-071-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83474 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vld3 intrinsics with 128-bit vectors.Bob Wilson2009-10-073-13/+92
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
* Rearrange code for selecting vld2 intrinsics. No functionality change.Bob Wilson2009-10-071-9/+14
| | | | | | | This is just to be more consistent with the forthcoming code for vld3/4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83470 91177308-0d34-0410-b5e6-96231b3b80d8
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-0729-97/+252
| | | | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not assume that the module is set.Devang Patel2009-10-071-15/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83462 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PR to this FIXME, looks like I didn't commit this change after all.Torok Edwin2009-10-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83457 91177308-0d34-0410-b5e6-96231b3b80d8
* Make getPointerTo return a const PointerType* rather thanDuncan Sands2009-10-071-1/+1
| | | | | | | an unqualified PointerType* because it seems more correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83454 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FreeInst to the "is a call" check for Insts that are calls, butEric Christopher2009-10-071-2/+2
| | | | | | | not intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83441 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix this comment. The loop header is the loop entry point.Dan Gohman2009-10-071-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83437 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PseudoSourceValues for constpool stuff on ELF (Darwin should use ↵Anton Korobeynikov2009-10-072-12/+34
| | | | | | | | something similar) and register spills. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83435 91177308-0d34-0410-b5e6-96231b3b80d8
* While we still have a MallocInst treat it as a call like any otherEric Christopher2009-10-071-0/+4
| | | | | | | | | | for inlining. When MallocInst goes away this code will be subsumed as part of calls and work just fine... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83434 91177308-0d34-0410-b5e6-96231b3b80d8
* Added bits of the ARM target assembler to llvm-mc to parse some load instructionKevin Enderby2009-10-061-1/+404
| | | | | | | | operands. Some parsing of arm memory operands for preindexing and postindexing forms including with register controled shifts. This is a work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83424 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for NEON vld2 operations on quad registers.Bob Wilson2009-10-064-1/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
* Use copyRegToReg hook to copy registers.Bob Wilson2009-10-061-6/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83421 91177308-0d34-0410-b5e6-96231b3b80d8
* r83391 was completely broken since Twines keep references to their inputs, andJeffrey Yasskin2009-10-061-4/+9
| | | | | | | | some of the inputs were temporaries. Here's a real fix for the miscompilation. Thanks to sabre for pointing out the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83417 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment typo.Bob Wilson2009-10-061-1/+1
| | | | | | | Patch by Johnny Chen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8
* Bugfix for the CommaSeparated option. The original code was adding the wholeNicolas Geoffray2009-10-061-0/+1
| | | | | | | | string at the end of the list, instead of the last comma-separated string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83405 91177308-0d34-0410-b5e6-96231b3b80d8
* Update CMake file.Ted Kremenek2009-10-061-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83404 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to handle debug info attached to an instruction.Devang Patel2009-10-064-6/+25
| | | | | | | This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83400 91177308-0d34-0410-b5e6-96231b3b80d8
* Instead of printing unnecessary basic block labels as labels inDan Gohman2009-10-0613-39/+14
| | | | | | | | | | | verbose-asm mode, print comments instead. This eliminates a non-comment difference between verbose-asm mode and non-verbose-asm mode. Also, factor out the relevant code out of all the targets and into target-independent code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83392 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR5112, a miscompilation on gcc-4.0.3. Patch by Collin Winter!Jeffrey Yasskin2009-10-061-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83391 91177308-0d34-0410-b5e6-96231b3b80d8
* remove predicate simplifier, it never got the last bugs beatenChris Lattner2009-10-061-2704/+0
| | | | | | | | | out of it, and jump threading, condprop and gvn are now getting most of the benefit. This was approved by Nicholas and Nicolas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83390 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove xs1b predicate since it is no longer needed to differentiate betweemRichard Osborne2009-10-064-33/+5
| | | | | | | xs1a and xs1b. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83383 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove xs1a subtarget. xs1a is a preproduction device used inRichard Osborne2009-10-067-98/+45
| | | | | | | | early development boards which is no longer supported in the XMOS toolchain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83381 91177308-0d34-0410-b5e6-96231b3b80d8
* Default to the xs1b subtargetRichard Osborne2009-10-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83380 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce and use convenience methods for getting pointer typesDuncan Sands2009-10-0621-58/+98
| | | | | | | | where the element is of a basic builtin type. For example, to get an i8* use getInt8PtrTy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83379 91177308-0d34-0410-b5e6-96231b3b80d8
* grammarJim Grosbach2009-10-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83378 91177308-0d34-0410-b5e6-96231b3b80d8
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