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* Loop Vectorize: optimize the vectorization of trunc(induction_var). The ↵Nadav Rotem2012-12-111-1/+13
| | | | | | truncation is now done on scalars. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169904 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the RelaxAll overrule in MCAssembler::fixupNeedsRelaxation,Eli Bendersky2012-12-111-3/+2
| | | | | | | | | | | | | because that method is only getting called for MCInstFragment. These fragments aren't even generated when RelaxAll is set, which is why the flag reference here is superfluous. Removing it simplifies the code with no harmful effects. An assertion is added higher up to make sure this path is never reached. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169886 91177308-0d34-0410-b5e6-96231b3b80d8
* Use an ArrayRef instead of a std::vector&.Rafael Espindola2012-12-111-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169881 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comment for load foldingJoel Jones2012-12-111-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169880 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Use explicitely aligned stores and loads with function argument shadow.Evgeniy Stepanov2012-12-111-8/+13
| | | | | | | | | | Use explicitely aligned store and load instructions to deal with argument and retval shadow. This matters when an argument's alignment is higher than __msan_param_tls alignment (which is the case with __m128i). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169859 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-1124-180/+176
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
* Holding my nose and moving the accumulation routine to GEPOperatorChandler Carruth2012-12-112-62/+3
| | | | | | | | | | | | | | | | | instead of the instruction. I've left a forwarding wrapper for the instruction so users with the instruction don't need to create a GEPOperator themselves. This lets us remove the copy of this code in instsimplify. I've looked at most of the other copies of similar code, and this is the only one I've found that is actually exactly the same. The one in InlineCost is very close, but it requires re-mapping non-constant indices through the cost analysis value simplification map. I could add direct support for this to the generic routine, but it seems overly specific. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169853 91177308-0d34-0410-b5e6-96231b3b80d8
* Hoist the GEP constant address offset computation to a common home onChandler Carruth2012-12-112-23/+34
| | | | | | | | | | | the GEP instruction class. This is part of the continued refactoring and cleaning of the infrastructure used by SROA. This particular operation is also done in a few other places which I'll try to refactor to share this implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169852 91177308-0d34-0410-b5e6-96231b3b80d8
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-112-13/+12
| | | | | | | instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169851 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-113-6/+7
| | | | | | | | | MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169850 91177308-0d34-0410-b5e6-96231b3b80d8
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-112-14/+19
| | | | | | | from EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169849 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-116-20/+20
| | | | | | | EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169848 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-111-4/+4
| | | | | | | EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169847 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-115-8/+8
| | | | | | | of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-112-8/+8
| | | | | | | instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169844 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-112-12/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169843 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-112-4/+4
| | | | | | | EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169842 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-112-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169841 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.Patrik Hagglund2012-12-112-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169840 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169839 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-114-12/+12
| | | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169838 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-1110-73/+68
| | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] Remove dependencies to intrinsics_gen I introduced in r169724.NAKAMURA Takumi2012-12-113-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169819 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-111-148/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR14565. Don't if-convert loops that have switch statements in them.Nadav Rotem2012-12-111-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169813 91177308-0d34-0410-b5e6-96231b3b80d8
* Stylistic tweak.Evan Cheng2012-12-111-9/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169811 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a miscompile in the DAG combiner. Previously, we would incorrectlyChandler Carruth2012-12-111-2/+6
| | | | | | | | | | | | | | | | | | | | | | | try to reduce the width of this load, and would end up transforming: (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32) to (truncate (zextload i32 <ptr+4> as i64) to i32) We lost the sext attached to the load while building the narrower i32 load, and replaced it with a zext because lshr always zext's the results. Instead, bail out of this combine when there is a conflict between a sextload and a zext narrowing. The rest of the DAG combiner still optimize the code down to the proper single instruction: movswl 6(...),%eax Which is exactly what we wanted. Previously we read past the end *and* missed the sign extension: movl 6(...), %eax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169802 91177308-0d34-0410-b5e6-96231b3b80d8
* Fall back to the selection dag isel to select tail calls.Chad Rosier2012-12-114-10/+14
| | | | | | | | | | | | | | | | | | | This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169796 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor out the abbreviation handling into a separate class thatEric Christopher2012-12-102-24/+57
| | | | | | | | | | | | controls each of the abbreviation sets (only a single one at the moment) and computes offsets separately as well for each set of DIEs. No real function change, ordering of abbreviations for the skeleton CU changed but only because we're computing in a separate order. Fix the testcase not to care. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169793 91177308-0d34-0410-b5e6-96231b3b80d8
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-108-41/+139
| | | | | | | | | | | | | | | | | | | | | | 1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimistically analyse Phi cyclesArnold Schwaighofer2012-12-101-41/+13
| | | | | | | | | | Analyse Phis under the starting assumption that they are NoAlias. Recursively look at their inputs. If they MayAlias/MustAlias there must be an input that makes them so. Addresses bug 14351. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169788 91177308-0d34-0410-b5e6-96231b3b80d8
* Defer call to InitSections until after MCContext has been initialized. IfLang Hames2012-12-103-2/+5
| | | | | | | | | InitSections is called before the MCContext is initialized it could cause duplicate temporary symbols to be emitted later (after context initialization resets the temporary label counter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169785 91177308-0d34-0410-b5e6-96231b3b80d8
* Rearrange vars and make comments more obvious.Eric Christopher2012-12-101-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169780 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove blank line at top of file.Eric Christopher2012-12-101-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169779 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a coding style nit.Eric Christopher2012-12-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169776 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable the loop vectorizer only on O2 and above. (Still disabled by default)Nadav Rotem2012-12-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169774 91177308-0d34-0410-b5e6-96231b3b80d8
* LegalizeDAG: Allow type promotion of scalar loadsTom Stellard2012-12-101-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169773 91177308-0d34-0410-b5e6-96231b3b80d8
* LegalizeDAG: Allow type promotion for scalar storesTom Stellard2012-12-101-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169772 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the LoopVectorizer into H and CPP.Nadav Rotem2012-12-102-951/+993
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169771 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup formatting, comments and naming.Eli Bendersky2012-12-101-21/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169762 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set HWEncoding field of registers. Use delete functionAkira Hatanaka2012-12-105-130/+30
| | | | | | | getMipsRegisterNumbering and use MCRegisterInfo::getEncodingValue instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169760 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the somewhat semantic term "split dwarf" it more matches what'sEric Christopher2012-12-102-30/+32
| | | | | | going on and makes a lot of the terminology in comments make more sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169758 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete the FissionCU.Eric Christopher2012-12-101-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169757 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder fission variables.Eric Christopher2012-12-102-5/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169756 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use a red zone for code coverage if the user specified `-mno-red-zone'.Bill Wendling2012-12-101-4/+17
| | | | | | | | | | The `-mno-red-zone' flag wasn't being propagated to the functions that code coverage generates. This allowed some of them to use the red zone when that wasn't allowed. <rdar://problem/12843084> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169754 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for reverse induction variables. For example:Nadav Rotem2012-12-101-90/+191
| | | | | | | | | while (i--) sum+=A[i]; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169752 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds statistics for other non-DWARF fragments emitted byEli Bendersky2012-12-101-2/+13
| | | | | | | | | | the assembler. This is useful in order to know how the numbers add up, since in particular the Align fragments account for a non-trivial portion of the emitted fragments (especially on -O0 which sets relax-all). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169747 91177308-0d34-0410-b5e6-96231b3b80d8
* Use GetUnderlyingObjects in mischedHal Finkel2012-12-101-92/+143
| | | | | | | | | | | | | | | | misched used GetUnderlyingObject in order to break false load/store dependencies, and the -enable-aa-sched-mi feature similarly relied on GetUnderlyingObject in order to ensure it is safe to use the aliasing analysis. Unfortunately, GetUnderlyingObject does not recurse through phi nodes, and so (especially due to LSR) all of these mechanisms failed for induction-variable-dependent loads and stores inside loops. This change replaces uses of GetUnderlyingObject with GetUnderlyingObjects (which will recurse through phi and select instructions) in misched. Andy reviewed, tested and simplified this patch; Thanks! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169744 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth2012-12-101-2/+1
| | | | | | Accidental commit... git svn betrayed me. Sorry for the noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169741 91177308-0d34-0410-b5e6-96231b3b80d8
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-101-1/+2
| | | | | | | | | | | | | | | | | | | Summary: Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169740 91177308-0d34-0410-b5e6-96231b3b80d8
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