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* Merge upstream to r134237 at Fri. 1st July 2011.Nowar Gu2011-07-01322-7427/+7889
|\ | | | | | | | | Conflicts: lib/Target/ARM/ARMCodeEmitter.cpp
| * Disable commit 134216 ("Add 134199 back, but disable the optimization when ↵Duncan Sands2011-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | the second copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out because gcc built with dragonegg is going into an infinite loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134237 91177308-0d34-0410-b5e6-96231b3b80d8
| * Another misuse of StringRef. MSVC is very sensitive to that kind of error.Francois Pichet2011-07-011-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134236 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix likely typo, reduce number of instruction name collisions.Nick Lewycky2011-07-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134235 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix use after free.Rafael Espindola2011-07-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134234 91177308-0d34-0410-b5e6-96231b3b80d8
| * Avoid DenseMap lookup.Rafael Espindola2011-07-011-6/+8
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134231 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix off by one error. I misunderstood the comment about killedAt.Rafael Espindola2011-07-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134229 91177308-0d34-0410-b5e6-96231b3b80d8
| * Check the liveinterval, not the kill flag.Rafael Espindola2011-07-011-7/+10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134228 91177308-0d34-0410-b5e6-96231b3b80d8
| * Don't inflate register classes used by inline asm.Jakob Stoklund Olesen2011-07-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The constraints are represented by the register class of the original virtual register created for the inline asm. If the register class were included in the operand descriptor, we might be able to do this. For now, just give up on regclass inflation when inline asm is involved. No test case, this bug hasn't happened yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134226 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve Mips back-end's handling of DBG_VALUE. Akira Hatanaka2011-07-015-23/+70
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve constant folding of undef for cmp and select operators.Dan Gohman2011-07-012-6/+11
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134223 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher2011-07-011-0/+9
| | | | | | | | | | | | | | | | | | supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve constant folding of undef for binary operators.Dan Gohman2011-07-011-4/+24
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134221 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the ARM 't' register constraint. And another testcaseEric Christopher2011-07-011-0/+5
| | | | | | | | | | | | | | | | | | for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
| * Switch SubtargetFeatures from std::string to StringRef.Evan Cheng2011-07-011-22/+19
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134219 91177308-0d34-0410-b5e6-96231b3b80d8
| * We'll return a null RC by default if we can't match.Eric Christopher2011-07-011-2/+1
| | | | | | | | | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add 134199 back, but disable the optimization when the second copy is a kill.Rafael Espindola2011-07-011-10/+100
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134216 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'x' constraint.Eric Christopher2011-07-011-0/+9
| | | | | | | | | | | | | | Part of rdar://9307836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove tabs.Bill Wendling2011-06-301-6/+6
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134212 91177308-0d34-0410-b5e6-96231b3b80d8
| * Capitalize the unsigned part of the initializer.Eric Christopher2011-06-301-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename Pair to RCPair lacking any better naming ideas.Eric Christopher2011-06-301-10/+10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve comment: Show the register the DWARF label is added to.Bill Wendling2011-06-301-1/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134209 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use the correct registers on X86_64.Bill Wendling2011-06-301-4/+4
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134208 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix a problem with fast-isel return values introduced in r134018.Jakob Stoklund Olesen2011-06-301-2/+3
| | | | | | | | | | | | | | | | | | We would put the return value from long double functions in the wrong register. This fixes gcc.c-torture/execute/conversion.c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134205 91177308-0d34-0410-b5e6-96231b3b80d8
| * Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-309-86/+26
| | | | | | | | | | | | | | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'h' constraint.Eric Christopher2011-06-302-1/+10
| | | | | | | | | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-302-0/+19
| | | | | | | | | | | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert my previous patch while I debug llvm-gcc bootstrap.Rafael Espindola2011-06-301-95/+10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134201 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add one more comment to the FDE verbose asm output.Bill Wendling2011-06-301-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134200 91177308-0d34-0410-b5e6-96231b3b80d8
| * Don't give up on coalescing A and B when we findRafael Espindola2011-06-301-10/+95
| | | | | | | | | | | | | | | | | | | | | | | | A = X B = X Instead, proceed as if we had found A = X B = A git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134199 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.Eric Christopher2011-06-301-7/+8
| | | | | | | | | | | | | | | | | | No functional change. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134198 91177308-0d34-0410-b5e6-96231b3b80d8
| * Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-308-51/+60
| | | | | | | | | | | | | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add comments to the FDE.Bill Wendling2011-06-301-5/+13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134196 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add more comments to the ASM output for the CIE's "moves".Bill Wendling2011-06-301-1/+20
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134194 91177308-0d34-0410-b5e6-96231b3b80d8
| * Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.cJakob Stoklund Olesen2011-06-301-3/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134193 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add comments to the ASM output to help understand the compact unwind and CIE ↵Bill Wendling2011-06-301-6/+61
| | | | | | | | | | | | tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134191 91177308-0d34-0410-b5e6-96231b3b80d8
| * Create a isFullCopy predicate.Rafael Espindola2011-06-301-5/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134189 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add r134057 back, but splice the predecessor after the successors phiRafael Espindola2011-06-303-11/+33
| | | | | | | | | | | | | | | | | | nodes. Original message: Let simplify cfg simplify bb with only debug and lifetime intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134182 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach2011-06-303-24/+7
| | | | | | | | | | | | | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
| * indvars -disable-iv-rewrite: handle cloning binary operators that cannot ↵Andrew Trick2011-06-301-3/+7
| | | | | | | | | | | | overflow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134177 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-302-19/+12
| | | | | | | | | | | | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-302-9/+10
| | | | | | | | | | | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134172 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove dead code.Rafael Espindola2011-06-301-88/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134148 91177308-0d34-0410-b5e6-96231b3b80d8
| * Kill dead code.Jim Grosbach2011-06-301-1/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134131 91177308-0d34-0410-b5e6-96231b3b80d8
| * Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| | | | | | | | | | | | | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134130 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix ARMSubtarget feature parsing.Evan Cheng2011-06-301-10/+7
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134129 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-3060-192/+238
| | | | | | | | | | | | | | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
| * Recognize the xstorerng alias for VIA PadLock's xstore instruction.Joerg Sonnenberger2011-06-301-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134126 91177308-0d34-0410-b5e6-96231b3b80d8
| * Reapply r134047 now that the world is ready for it.Jakob Stoklund Olesen2011-06-303-138/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will sometimes choose live range split points next to interference instead of always splitting next to a register point. That means spill code can now appear almost anywhere, and it was necessary to fix code that didn't expect that. The difficult places were: - Between a CALL returning a value on the x87 stack and the corresponding FpPOP_RETVAL (was FpGET_ST0). Probably also near x87 inline assembly, but that didn't actually show up in testing. - Between a CALL popping arguments off the stack and the corresponding ADJCALLSTACKUP. Both are fixed now. The only place spill code can't appear is after terminators, see SplitAnalysis::getLastSplitPoint. Original commit message: Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art. This function has to deal with a lot of special cases, and the old version got it wrong sometimes. In particular, it would sometimes leave multiple uses in the stack interval in a single block. That causes bad code with multiple reloads in the same basic block. The new version handles block entry and exit in a single pass. It first eliminates all the easy cases, and then goes on to create a local interval for the blocks with difficult interference. Previously, we would only create the local interval for completely isolated blocks. It can happen that the stack interval becomes completely empty because we could allocate a register in all edge bundles, and the new local intervals deal with the interference. The empty stack interval is harmless, but we need to remove a SplitKit assertion that checks for empty intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134125 91177308-0d34-0410-b5e6-96231b3b80d8
| * indvars -disable-iv-rewrite: handle an edge case involving identity phis.Andrew Trick2011-06-301-3/+8
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134124 91177308-0d34-0410-b5e6-96231b3b80d8
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