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* SLPVectorizer: Fix PR16777. PHInodes may use multiple extracted values that c...Nadav Rotem2013-08-021-10/+13
* Fixes ARM LNT bot from SLP change in O3Renato Golin2013-08-021-6/+8
* Bugfix for making the DWARF debug strings and labels to code emitted as secre...Carlo Kok2013-08-021-0/+4
* Pacify GCC, which worries about falling off the end of the switch.Duncan Sands2013-08-021-0/+2
* Fix dereferencing end iterator in SimplifyCFG. Patch by Ye Mei.Alexey Samsonov2013-08-021-5/+8
* Revert r187597, "Bugfix for making the DWARF debug strings and labels to code...NAKAMURA Takumi2013-08-021-4/+0
* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-022-7/+16
* Teach InstructionSimplify about pointer address spacesMatt Arsenault2013-08-021-4/+9
* [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,Akira Hatanaka2013-08-012-22/+11
* Teach getOrEnforceKnownAlignment about address spacesMatt Arsenault2013-08-011-4/+5
* Move the optlevel check to the frontend.Nadav Rotem2013-08-011-1/+1
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-014-5/+7
* Fixed the Intel-syntax X86 disassembler to respect the (existing) option for ...Daniel Malea2013-08-013-13/+54
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-011-0/+52
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-012-16/+7
* DebugInfo: Emit definitions for types with no members.David Blaikie2013-08-011-7/+3
* Bugfix for making the DWARF debug strings and labels to code emitted as secre...Carlo Kok2013-08-011-0/+4
* Only enable SLP-vectorization on O3 builds.Nadav Rotem2013-08-011-1/+1
* R600: Add 64-bit float load/store supportTom Stellard2013-08-018-23/+139
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-011-1/+1
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-012-0/+16
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-012-54/+278
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-016-58/+277
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-011-1/+25
* Moving definition of MnemonicContainsDot field from class Instruction to clas...Vladimir Medic2013-08-012-1/+1
* AArch64: add initial NEON supportTim Northover2013-08-0117-35/+2649
* XCore target: Fix Vararg handlingRobert Lytton2013-08-011-12/+14
* XCore target: Add byval handlingRobert Lytton2013-08-011-11/+63
* Xcore targetRobert Lytton2013-08-011-6/+9
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-2/+7
* Add an omitted IsCall=1.Reed Kotler2013-08-011-0/+1
* Option parsing: add support for alias arguments.Hans Wennborg2013-07-311-2/+20
* 80-colNadav Rotem2013-07-311-9/+14
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-312-0/+30
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-314-60/+19
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-314-19/+23
* R600: Do not mergevector after a vector reg is usedVincent Lejeune2013-07-311-1/+10
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+5
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-314-19/+60
* R600: Don't mix LDS and non-LDS instructions in the same groupVincent Lejeune2013-07-311-0/+4
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-07-314-23/+19
* R600: Remove predicated_break instVincent Lejeune2013-07-314-59/+7
* Reject bitcasts between address spaces with different sizesMatt Arsenault2013-07-311-20/+104
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-312-3/+21
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-315-31/+31
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-319-81/+137
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-314-136/+119
* Fixed assertion in Extract128BitVector()Elena Demikhovsky2013-07-311-1/+2
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-314-79/+193
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-316-181/+811
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