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* Fix Android.mk.Nowar Gu2011-07-027-6/+10
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* Merge upstream to r134306 at Sat. 2nd July 2011.Nowar Gu2011-07-02105-440/+723
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| * indvars -disable-iv-rewrite: bug fix involving weird geps and related cleanup.Andrew Trick2011-07-021-46/+51
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134306 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use a new strategy for preventing eviction loops in RAGreedy.Jakob Stoklund Olesen2011-07-021-57/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every live range is assigned a cascade number the first time it is involved in an eviction. As the evictor, it gets a new cascade number. Every evictee is assigned the same cascade number as the evictor. Eviction is prohibited if the evictor has a lower assigned cascade number than the evictee. This means that assigned cascade numbers are monotonically increasing with every eviction, yet they are bounded by NextCascade which can only be incremented by new live ranges. Thus, infinite loops cannot happen, but eviction cascades can still be triggered by new live ranges as we want. Thanks to Andy for explaining this to me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134303 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add getFeatureBits to extract feature bits for a given CPU.Evan Cheng2011-07-021-0/+8
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134298 91177308-0d34-0410-b5e6-96231b3b80d8
| * Take a stab at fixing the llvm-x86_64-linux-checks failure.Cameron Zwarich2011-07-011-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134287 91177308-0d34-0410-b5e6-96231b3b80d8
| * TargetConstant immediates won't be placed into registers so tightenEric Christopher2011-07-011-3/+4
| | | | | | | | | | | | | | | | | | up the valid constant check earlier. rdar://9692967 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134286 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add initial *-*-rtems* target, from Joel SherrillDouglas Gregor2011-07-011-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134282 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-0153-58/+55
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add MCSubtargetInfo target registry stuff.Evan Cheng2011-07-011-0/+28
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134279 91177308-0d34-0410-b5e6-96231b3b80d8
| * Teach IVUsers to stop at non-affine expressions unless they are bothDan Gohman2011-07-011-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | outside the loop and reducible. This more completely hides them from LSR, which isn't usually able to do anything meaningful with non-affine expressions anyway, and this consequently hides them from SCEVExpander, which is acutely unprepared for non-affine expressions. Replace test/CodeGen/X86/lsr-nonaffine.ll with a new test that tests the new behavior. This works around the bug in PR10117 / rdar://problem/9633149, and is generally an improvement besides. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134268 91177308-0d34-0410-b5e6-96231b3b80d8
| * Generalize @llvm.ctlz, @llvm.cttz, and @llvm.ctpop to work on vectors of ↵Owen Anderson2011-07-011-2/+6
| | | | | | | | | | | | integers, and fix the one optimization pass that I'm aware of that needs updating for this. At least one current target, ARM NEON, can implement these operations on vectors directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134265 91177308-0d34-0410-b5e6-96231b3b80d8
| * Calling-convention specifications for illegal types are no-ops. Simplify ↵Eli Friedman2011-07-011-30/+11
| | | | | | | | | | | | based on this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134264 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARMv7M vs. ARMv7E-M support.Jim Grosbach2011-07-016-49/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-0133-76/+77
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
| * - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-0128-28/+201
| | | | | | | | | | | | | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix off-by-one error.Jim Grosbach2011-07-011-1/+1
| | | | | | | | | | | | (low two bits always zero, so off by one bit of encoded value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134247 91177308-0d34-0410-b5e6-96231b3b80d8
| * Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-0127-51/+85
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
| * Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-014-55/+18
| | | | | | | | | | | | | | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
| * Eliminate one extra conversion.Evan Cheng2011-07-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134240 91177308-0d34-0410-b5e6-96231b3b80d8
* | Fix Android.mk.Nowar Gu2011-07-0216-34/+60
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* | Merge upstream to r134237 at Fri. 1st July 2011.Nowar Gu2011-07-01322-7427/+7889
|\ \ | |/ | | | | | | Conflicts: lib/Target/ARM/ARMCodeEmitter.cpp
| * Disable commit 134216 ("Add 134199 back, but disable the optimization when ↵Duncan Sands2011-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | the second copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out because gcc built with dragonegg is going into an infinite loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134237 91177308-0d34-0410-b5e6-96231b3b80d8
| * Another misuse of StringRef. MSVC is very sensitive to that kind of error.Francois Pichet2011-07-011-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134236 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix likely typo, reduce number of instruction name collisions.Nick Lewycky2011-07-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134235 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix use after free.Rafael Espindola2011-07-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134234 91177308-0d34-0410-b5e6-96231b3b80d8
| * Avoid DenseMap lookup.Rafael Espindola2011-07-011-6/+8
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134231 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix off by one error. I misunderstood the comment about killedAt.Rafael Espindola2011-07-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134229 91177308-0d34-0410-b5e6-96231b3b80d8
| * Check the liveinterval, not the kill flag.Rafael Espindola2011-07-011-7/+10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134228 91177308-0d34-0410-b5e6-96231b3b80d8
| * Don't inflate register classes used by inline asm.Jakob Stoklund Olesen2011-07-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The constraints are represented by the register class of the original virtual register created for the inline asm. If the register class were included in the operand descriptor, we might be able to do this. For now, just give up on regclass inflation when inline asm is involved. No test case, this bug hasn't happened yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134226 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve Mips back-end's handling of DBG_VALUE. Akira Hatanaka2011-07-015-23/+70
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve constant folding of undef for cmp and select operators.Dan Gohman2011-07-012-6/+11
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134223 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher2011-07-011-0/+9
| | | | | | | | | | | | | | | | | | supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve constant folding of undef for binary operators.Dan Gohman2011-07-011-4/+24
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134221 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the ARM 't' register constraint. And another testcaseEric Christopher2011-07-011-0/+5
| | | | | | | | | | | | | | | | | | for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
| * Switch SubtargetFeatures from std::string to StringRef.Evan Cheng2011-07-011-22/+19
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134219 91177308-0d34-0410-b5e6-96231b3b80d8
| * We'll return a null RC by default if we can't match.Eric Christopher2011-07-011-2/+1
| | | | | | | | | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134217 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add 134199 back, but disable the optimization when the second copy is a kill.Rafael Espindola2011-07-011-10/+100
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134216 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'x' constraint.Eric Christopher2011-07-011-0/+9
| | | | | | | | | | | | | | Part of rdar://9307836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove tabs.Bill Wendling2011-06-301-6/+6
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134212 91177308-0d34-0410-b5e6-96231b3b80d8
| * Capitalize the unsigned part of the initializer.Eric Christopher2011-06-301-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134211 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename Pair to RCPair lacking any better naming ideas.Eric Christopher2011-06-301-10/+10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134210 91177308-0d34-0410-b5e6-96231b3b80d8
| * Improve comment: Show the register the DWARF label is added to.Bill Wendling2011-06-301-1/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134209 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use the correct registers on X86_64.Bill Wendling2011-06-301-4/+4
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134208 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix a problem with fast-isel return values introduced in r134018.Jakob Stoklund Olesen2011-06-301-2/+3
| | | | | | | | | | | | | | | | | | We would put the return value from long double functions in the wrong register. This fixes gcc.c-torture/execute/conversion.c git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134205 91177308-0d34-0410-b5e6-96231b3b80d8
| * Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-309-86/+26
| | | | | | | | | | | | | | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for the 'h' constraint.Eric Christopher2011-06-302-1/+10
| | | | | | | | | | | | | | Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134203 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add target a target hook to get the register number used by the compact unwindBill Wendling2011-06-302-0/+19
| | | | | | | | | | | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134202 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert my previous patch while I debug llvm-gcc bootstrap.Rafael Espindola2011-06-301-95/+10
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134201 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add one more comment to the FDE verbose asm output.Bill Wendling2011-06-301-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134200 91177308-0d34-0410-b5e6-96231b3b80d8
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