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* Add 'landingpad' instructions to the list of instructions to ignore.Bill Wendling2012-05-041-7/+9
| | | | | | | Also combine the code in the 'assert' statement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156155 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify shuffle narrowing code a bit. No functional change intended.Craig Topper2012-05-041-22/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen2012-05-046-121/+30
| | | | | | This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SuperRegClassIterator for findRepresentativeClass().Jakob Stoklund Olesen2012-05-041-26/+15
| | | | | | | | The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156147 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize SparcInstrInfo before SparcTargetLowering.Jakob Stoklund Olesen2012-05-042-2/+3
| | | | | | | The TargetLowering construction needs to use a valid TargetRegisterInfo instance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156146 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SuperRegClassIterator class.Jakob Stoklund Olesen2012-05-041-15/+13
| | | | | | | | This iterator class provides a more abstract interface to the (Idx, Mask) lists of super-registers for a register class. The layout of the tables shouldn't be exposed to clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156144 91177308-0d34-0410-b5e6-96231b3b80d8
* A pile of long over-due refactorings here. There are some very, *very*Chandler Carruth2012-05-043-43/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | minor behavior changes with this, but nothing I have seen evidence of in the wild or expect to be meaningful. The real goal is unifying our logic and simplifying the interfaces. A summary of the changes follows: - Make 'callIsSmall' actually accept a callsite so it can handle intrinsics, and simplify callers appropriately. - Nuke a completely bogus declaration of 'callIsSmall' that was still lurking in InlineCost.h... No idea how this got missed. - Teach the 'isInstructionFree' about the various more intelligent 'free' heuristics that got added to the inline cost analysis during review and testing. This mostly surrounds int->ptr and ptr->int casts. - Switch most of the interesting parts of the inline cost analysis that were essentially computing 'is this instruction free?' to use the code metrics routine instead. This way we won't keep duplicating logic. All of this is motivated by the desire to allow other passes to compute a roughly equivalent 'cost' metric for a particular basic block as the inline cost analysis. Sadly, re-using the same analysis for both is really messy because only the actual inline cost analysis is ever going to go to the contortions required for simplification, SROA analysis, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156140 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-0/+30
| | | | | | TargetRegisterClass now gives access to the necessary tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-033-42/+99
| | | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor the logic for testing whether a basic block is viable for codeChandler Carruth2012-05-031-14/+21
| | | | | | | | | | | extraction into a public interface. Also clean it up and apply it more consistently such that we check for landing pads *anywhere* in the extracted code, not just in single-block extraction. This will be used to guide decisions in passes that are planning to eventually perform a round of code extraction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156114 91177308-0d34-0410-b5e6-96231b3b80d8
* remove calls to calloc if the allocated memory is not used (it was already ↵Nuno Lopes2012-05-032-3/+3
| | | | | | | | being done for malloc) fix a few typos found by Chad in my previous commit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156110 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for target dependent Hexagon VLIW packetizer.Sirish Pande2012-05-0314-93/+4967
| | | | | | This patch creates and optimizes packets as per Hexagon ISA rules. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for calloc to objectsize loweringNuno Lopes2012-05-032-5/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156102 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-039-1339/+4107
| | | | | | This adds new instructions for Hexagon V4 architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
* replace 'break's with 'return 0' in visitCallInst code for objectsize, since ↵Nuno Lopes2012-05-031-5/+5
| | | | | | | | there is no need to fallback to visitCallSite. This gives a 0.9% in a test case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156069 91177308-0d34-0410-b5e6-96231b3b80d8
* Use 'unsigned' instead of 'int' in a few places dealing with counts of ↵Craig Topper2012-05-031-3/+3
| | | | | | vector elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the ↵Craig Topper2012-05-032-21/+36
| | | | | | lower half correctly. Missed in r155982. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-031-15/+16
| | | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156048 91177308-0d34-0410-b5e6-96231b3b80d8
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-033-8/+40
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace cleanup.Bill Wendling2012-05-021-87/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156034 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson2012-05-021-0/+18
| | | | | | just like it now knows for FMULs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156029 91177308-0d34-0410-b5e6-96231b3b80d8
* For Intel Atom, use ILP scheduling always, instead of ILP for 64 bitPreston Gurd2012-05-021-4/+4
| | | | | | | | | and Hybrid for 32 bit, since benchmarks show ILP scheduling is better most of the time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the Intel Atom detection code to recognizePreston Gurd2012-05-022-3/+5
| | | | | | | | Lincroft and Medfield. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson2012-05-021-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156023 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
* Move llvm-tblgen's StringMatcher into the TableGen library so it canDouglas Gregor2012-05-022-0/+150
| | | | | | | be used by clang-tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156000 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-024-68/+171
| | | | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r155853Manman Ren2012-05-021-16/+0
| | | | | | | | | The commit is intended to fix rdar://10961709. But it is the root cause of PR12720. Revert it for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
* [tsan] typo and style (thanks to Nick Lewycky)Kostya Serebryany2012-05-021-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155986 91177308-0d34-0410-b5e6-96231b3b80d8
* The value held in the vector may be RAUW'ed by some of the canonicalizationBill Wendling2012-05-021-2/+3
| | | | | | | | methods. Use a weak value handle to keep up with this. PR12245 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155984 91177308-0d34-0410-b5e6-96231b3b80d8
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-021-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support ↵Craig Topper2012-05-024-36/+90
| | | | | | for AsmPrinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155982 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the implementation of MachOObjectFile::isSectionZeroInit so it follows ↵Eli Friedman2012-05-021-4/+6
| | | | | | the MachO spec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155976 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Naming conventions.Jim Grosbach2012-05-011-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155960 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded break.Jakub Staszak2012-05-011-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155959 91177308-0d34-0410-b5e6-96231b3b80d8
* Use dyn_cast instead of checking opcode and cast.Jakub Staszak2012-05-011-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155957 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing spaces.Jakub Staszak2012-05-011-43/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155956 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip the pointer casts off of allocas so that the selection DAG can find them.Bill Wendling2012-05-011-1/+1
| | | | | | | PR10799 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155954 91177308-0d34-0410-b5e6-96231b3b80d8
* Target independent Hexagon Packetizer fix.Sirish Pande2012-05-011-55/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155947 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+11
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-4/+16
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch marks the X86 floating point stack registers ST0-ST7 as reservedPreston Gurd2012-05-011-0/+10
| | | | | | | | | | | in order to avoid assertion failures in the register scavenger. The assertion failures were “Bad machine code: Using an undefined physical register” and “Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor!”. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155930 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Unknown assembler directives are now hard errors.Jim Grosbach2012-05-011-1/+1
| | | | | | | | | | | | | | | | Previously, an unsupported/unknown assembler directive issued a warning. That's generally unsafe, and inconsistent with the behaviour of pretty much every system assembler. Now that the MC assemblers are mature enough to be the default on multiple targets, it's reasonable to issue errors for these. For target or platform directives that need to stay warnings, we should add explicit handlers for them in, e.g., ELFAsmParser.cpp, DarwinAsmParser.cpp, et. al., and issue the warning there. rdar://9246275 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155926 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Remove errant EatToEndOfStatement() in asm parser.Jim Grosbach2012-05-011-3/+1
| | | | | | | | | | | | The caller is already responsible for eating any additional input on the line. Putting an additional EatToEndOfStatement() in ParseStatement() causes an entire extra statement to be consumed when treating warnings as errors. For example, test/MC/macros.s will assert() because the .endmacro directive is missed as a result. rdar://11355843 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155925 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: optimization for max-like structManman Ren2012-05-011-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | This patch will optimize the following cases on X86 (a > b) ? (a-b) : 0 (a >= b) ? (a-b) : 0 (b < a) ? (a-b) : 0 (b <= a) ? (a-b) : 0 FROM movl %edi, %ecx subl %esi, %ecx cmpl %edi, %esi movl $0, %eax cmovll %ecx, %eax TO xorl %eax, %eax subl %esi, %edi cmovll %eax, %edi movl %edi, %eax rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155919 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Use StackRegister instead of FrameRegister in getFrameIndexReference ↵Alexey Samsonov2012-05-012-0/+14
| | | | | | (to generate debug info for local variables) if stack needs realignment git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155917 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MipsDisassembler classes into an anonymous namespace.Benjamin Kramer2012-05-011-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155915 91177308-0d34-0410-b5e6-96231b3b80d8
* Value-initialize global to avoid global construction.Benjamin Kramer2012-05-011-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155909 91177308-0d34-0410-b5e6-96231b3b80d8
* RuntimeDyld cleanup:Eli Bendersky2012-05-014-65/+77
| | | | | | | | | | | | | - Improved parameter names for clarity - Added comments - emitCommonSymbols should return void because its return value is not being used anywhere - Attempt to reduce the usage of the RelocationValueRef type. Restricts it for a single goal and may serve as a step for eventual removal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155908 91177308-0d34-0410-b5e6-96231b3b80d8
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