aboutsummaryrefslogtreecommitdiffstats
path: root/lib
Commit message (Collapse)AuthorAgeFilesLines
* Add exception necessitated by 133938.Jim Grosbach2011-06-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133939 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly carry set/clear condition code aliases for 'hi/lo'Jim Grosbach2011-06-271-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133938 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler support for ldmfd/stmfd mnemonics.Jim Grosbach2011-06-271-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler support for vpush/vpop.Jim Grosbach2011-06-271-0/+9
| | | | | | | | | | | Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple writeback instructions w/ SP as the base pointer. rdar://9683231 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Assembly syntax support for arithmetic implied dest operand.Jim Grosbach2011-06-271-7/+25
| | | | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: sub r2, r2, #6 sub r2, #6 rdar://9682597 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
* The index stored in the RegDefIter is one after the current index. When ↵Owen Anderson2011-06-271-1/+1
| | | | | | getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133923 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-2768-121/+130
| | | | | | | into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
* pre-RA-sched: Cleanup register pressure tracking.Andrew Trick2011-06-272-16/+4
| | | | | | | | | Removed the check that peeks past EXTRA_SUBREG, which I don't think makes sense any more. Intead treat it as a normal register def. No significant affect on x86 or ARM benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133917 91177308-0d34-0410-b5e6-96231b3b80d8
* Track live-out physical registers in MachineDCE.Jakob Stoklund Olesen2011-06-271-3/+8
| | | | | | Patch by Sanjoy Das! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133910 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach one piece of scalarrepl to handle lifetime markers. When transforming anNick Lewycky2011-06-271-13/+37
| | | | | | | | | alloca that only holds a copy of a global and we're going to replace the users of the alloca with that global, just nuke the lifetime intrinsics. Part of PR10121. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133905 91177308-0d34-0410-b5e6-96231b3b80d8
* Move onlyUsedByLifetimeMarkers to ValueTracking so that it can be used by otherNick Lewycky2011-06-272-16/+17
| | | | | | | passes as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133904 91177308-0d34-0410-b5e6-96231b3b80d8
* Grow the X86FloatingPoint register map to hold 16 registers.Jakob Stoklund Olesen2011-06-271-5/+15
| | | | | | | This allows for more live scratch registers which is needed to handle live ST registers before return and inline asm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133903 91177308-0d34-0410-b5e6-96231b3b80d8
* Distinguish early clobber output operands from clobbered registers.Jakob Stoklund Olesen2011-06-275-5/+8
| | | | | | | | | | | | | | | | | | | | | | Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we now use two different asm operand kinds. The new Kind_Clobber is treated identically to the old Kind_RegDefEarlyClobber for now, but x87 floating point stack inline assembly does care about the difference. This will pop a register off the stack: asm("fstp %st" : : "t"(x) : "st"); While this will pop the input and push an output: asm("fst %st" : "=&t"(r) : "t"(x)); We need to know if ST0 was a clobber or an output operand, and we can't depend on <dead> flags for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133902 91177308-0d34-0410-b5e6-96231b3b80d8
* Decode and pretty print inline asm operand descriptors.Jakob Stoklund Olesen2011-06-271-1/+22
| | | | | | | | | | The INLINEASM MachineInstrs have an immediate operand describing each original inline asm operand. Decode the bits in MachineInstr::print() so it is easier to read: INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133901 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused methods.Rafael Espindola2011-06-261-13/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133900 91177308-0d34-0410-b5e6-96231b3b80d8
* There is only one register coalescer. Merge it into the base class andRafael Espindola2011-06-268-197/+151
| | | | | | remove the analysis group. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133899 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge SimpleRegisterCoalescing.cpp into RegisterCoalescer.cpp.Rafael Espindola2011-06-263-1541/+1523
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133897 91177308-0d34-0410-b5e6-96231b3b80d8
* merge SimpleRegisterCoalescing.h into RegisterCoalescer.h.Rafael Espindola2011-06-264-156/+129
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133896 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterCoalescer.h to lib/CodeGen.Rafael Espindola2011-06-269-9/+253
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133895 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary wrapper.Rafael Espindola2011-06-262-27/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133886 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace dyn_cast<> with cast<> since the cast is already guarded by the ↵Chad Rosier2011-06-251-1/+1
| | | | | | necessary check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133874 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Reverting implementation of i8.Dan Bailey2011-06-257-296/+73
| | | | | | | | | | The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
* Object: Add proper error handling.Michael J. Spencer2011-06-255-192/+425
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133872 91177308-0d34-0410-b5e6-96231b3b80d8
* Make Binary the parent of ObjectFile and update children to new interface.Michael J. Spencer2011-06-255-152/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133870 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Binary class. This is a cleaner parent than ObjectFile.Michael J. Spencer2011-06-252-0/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133869 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Object/Error.Michael J. Spencer2011-06-252-0/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133868 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable tail call optimization in the presence of a byval (x86-32 and x86-64).Chad Rosier2011-06-251-0/+4
| | | | | | <rdar://problem/9483883> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133858 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak CMake buildDouglas Gregor2011-06-251-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133853 91177308-0d34-0410-b5e6-96231b3b80d8
* Add include guard.Evan Cheng2011-06-241-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133847 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename TargetDesc to MCTargetDescEvan Cheng2011-06-246-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133846 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor MachO relocation generaration into the Target directories.Jim Grosbach2011-06-244-985/+904
| | | | | | | | | | Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
* The scheduler needs to be aware on the existence of untyped nodes when it ↵Owen Anderson2011-06-241-1/+2
| | | | | | performs type propagation for EXTRACT_SUBREG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133838 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix cmake build.Rafael Espindola2011-06-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133830 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix struct member's scope. Patch by Xi Wang.Devang Patel2011-06-241-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133828 91177308-0d34-0410-b5e6-96231b3b80d8
* Hoist simple check above more complex checking to avoid unnecessary Chad Rosier2011-06-241-5/+5
| | | | | | | overheads. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133824 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert unintentional check-in.Devang Patel2011-06-242-81/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133822 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle debug info for i128 constants.Devang Patel2011-06-249-38/+119
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add MCRegisterInfo registration machinery. Also added x86 registration ↵Evan Cheng2011-06-242-0/+16
| | | | | | | | | routines. - Rename TargetRegisterDesc to MCRegisterDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM movw/movt fixups need to mask the high bits.Jim Grosbach2011-06-241-3/+6
| | | | | | | | | | The fixup value comes in as the whole 32-bit value, so for the lo16 fixup, the upper bits need to be masked off. Previously we assumed the masking had already been done and asserted. rdar://9635991 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
* tidy up whitespace.Jim Grosbach2011-06-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133815 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Add support for i8 type and introduce associated .b8 registersDan Bailey2011-06-247-15/+291
| | | | | | | | The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133814 91177308-0d34-0410-b5e6-96231b3b80d8
* The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier2011-06-241-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Add preliminary support for outputting debug information in the form ofJustin Holewinski2011-06-241-0/+97
| | | | | | | | | | .file and .loc directives. Ideally, we would utilize the existing support in AsmPrinter for this, but I cannot find a way to get .file and .loc directives to print without the rest of the associated DWARF sections, which ptxas cannot handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133812 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the chain input of nodes that load the address of a function. This changeAkira Hatanaka2011-06-241-4/+1
| | | | | | | | | | | enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a pre-existing node instead of redundantly create a new node every time it is called. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup info for Thumb2 unconditional branch.Jim Grosbach2011-06-241-0/+1
| | | | | | rdar://9667872 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133808 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent generation of redundant addiu instructions that compute address of Akira Hatanaka2011-06-241-1/+2
| | | | | | | | | static variables or functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133803 91177308-0d34-0410-b5e6-96231b3b80d8
* PTX: Re-work target sm/compute selection and add some basic GPUJustin Holewinski2011-06-246-47/+121
| | | | | | targets: g80, gt200, gf100(fermi) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133799 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyRafael Espindola2011-06-241-14/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133798 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that bb with phis are not considered simple, duplicate them even ifRafael Espindola2011-06-241-12/+18
| | | | | | we cannot duplicate to every predecessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133797 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify now that blocks with phis are not considered simple.Rafael Espindola2011-06-241-15/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133793 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-04-01 07:00:50 +0000