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* Drop <def,dead> flags when merging into an unused lane.Jakob Stoklund Olesen2012-10-131-4/+9
| | | | | | | | | | | | The new coalescer can merge a dead def into an unused lane of an otherwise live vector register. Clear the <dead> flag when that happens since the flag refers to the full virtual register which is still live after the partial dead def. This fixes PR14079. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165877 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate strchr and strrchr optimizationsMeador Inge2012-10-132-91/+86
| | | | | | | This patch migrates the strchr and strrchr optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165875 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Migrate strcat and strncat optimizationsMeador Inge2012-10-132-101/+107
| | | | | | | This patch migrates the strcat and strncat optimizations from the simplify-libcalls pass into the instcombine library call simplifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165874 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement new LibCallSimplifier classMeador Inge2012-10-135-36/+299
| | | | | | | | | | | | | | | | This patch implements the new LibCallSimplifier class as outlined in [1]. In addition to providing the new base library simplification infrastructure, all the fortified library call simplifications were moved over to the new infrastructure. The rest of the library simplification optimizations will be moved over with follow up patches. NOTE: The original fortified library call simplifier located in the SimplifyFortifiedLibCalls class was not removed because it is still used by CodeGenPrepare. This class will eventually go away too. [1] http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-August/052283.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165873 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow for loops in LiveIntervals::pruneValue().Jakob Stoklund Olesen2012-10-131-29/+32
| | | | | | | | | | | | | | It is possible that the live range of the value being pruned loops back into the kill MBB where the search started. When that happens, make sure that the beginning of KillMBB is also pruned. Instead of starting a DFS at KillMBB and skipping the root of the search, start a DFS at each KillMBB successor, and allow the search to loop back to KillMBB. This fixes PR14078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165872 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix accidentally swapped operands.Benjamin Kramer2012-10-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165871 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach SROA to cope with wrapper aggregates. These show up a lot in ABIChandler Carruth2012-10-131-3/+33
| | | | | | | | | | | | | | | | | | | | | | | type coercion code, especially when targetting ARM. Things like [1 x i32] instead of i32 are very common there. The goal of this logic is to ensure that when we are picking an alloca type, we look through such wrapper aggregates and across any zero-length aggregate elements to find the simplest type possible to form a type partition. This logic should (generally speaking) rarely fire. It only ends up kicking in when an alloca is accessed using two different types (for instance, i32 and float), and the underlying alloca type has wrapper aggregates around it. I noticed a significant amount of this occurring looking at stepanov_abstraction generated code for arm, and suspect it happens elsewhere as well. Note that this doesn't yet address truly heinous IR productions such as PR14059 is concerning. Those result in mismatched *sizes* of types in addition to mismatched access and alloca types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165870 91177308-0d34-0410-b5e6-96231b3b80d8
* Speculatively harden the conversion logic. I have no idea if this willChandler Carruth2012-10-131-0/+11
| | | | | | | | | help the dragonegg builders, and no test case at this point, but this was one dimly plausible case I spotted by inspection. Hopefully will get a testcase from those bots soon-ish, and will tidy this up with proper testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165869 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Promote i8 cmov when both operands are coming from truncates of the ↵Benjamin Kramer2012-10-131-0/+15
| | | | | | | | | | | | | | same width. X86 doesn't have i8 cmovs so isel would emit a branch. Emitting branches at this level is often not a good idea because it's too late for many optimizations to kick in. This solution doesn't add any extensions (truncs are free) and tries to avoid introducing partial register stalls by filtering direct copyfromregs. I'm seeing a ~10% speedup on reading a random .png file with libpng15 via graphicsmagick on x86_64/westmere, but YMMV depending on the microarchitecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165868 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence a warning in -assert builds.Chandler Carruth2012-10-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165867 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up how we rewrite loads and stores to the whole alloca. When theseChandler Carruth2012-10-131-5/+49
| | | | | | | | | | | | are single value types, the load and store should be directly based upon the alloca and then bitcasting can fix the type as needed afterward. This might in theory improve some of the IR coming out of SROA, but I don't expect big changes yet and don't have any test cases on hand. This is really just a cleanup/refactoring patch. The next patch will cause this code path to be hit a lot more, actually get SROA to promote more allocas and include several more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165864 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Remove the MatchInstruction() function. Previously, this wasChad Rosier2012-10-135-46/+45
| | | | | | | | | | | | | the interface between the front-end and the MC layer when parsing inline assembly. Unfortunately, this is too deep into the parsing stack. Specifically, we're unable to handle target-independent assembly (i.e., assembly directives, labels, etc.). Note the MatchAndEmitInstruction() isn't the correct abstraction either. I'll be exposing target-independent hooks shortly, so this is really just a cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165858 91177308-0d34-0410-b5e6-96231b3b80d8
* Check section type rather than assuming it's code when emitting sections ↵Andrew Kaylor2012-10-121-1/+7
| | | | | | while processing relocations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165854 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: tail-call inside a function where part of a byval argument is on caller'sManman Ren2012-10-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | local frame causes problem. For example: void f(StructToPass s) { g(&s, sizeof(s)); } will cause problem with tail-call since part of s is passed via registers and saved in f's local frame. When g tries to access s, part of s may be corrupted since f's local frame is popped out before the tail-call. The current fix is to disable tail-call if getVarArgsRegSaveSize is not 0 for the caller. This is a conservative approach, if we can prove the address of s or part of s is not taken and passed to g, it should be okay to perform tail-call. rdar://12442472 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165853 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Capitalize per coding standard.Chad Rosier2012-10-121-19/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165847 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Mark VSELECT as 'expand'.Jim Grosbach2012-10-121-0/+1
| | | | | | | | | | | | | The backend already pattern matches to form VBSL when it can. We may want to teach it to use the vbsl intrinsics at some point to prevent machine licm from mucking with this, but using the Expand is completely correct. http://llvm.org/bugs/show_bug.cgi?id=13831 http://llvm.org/bugs/show_bug.cgi?id=13961 Patch by Peter Couperus <peter.couperus@st.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165845 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Use the new API introduced in r165830 in lieu of theChad Rosier2012-10-124-37/+18
| | | | | | | | MapAndConstraints vector. Also remove the unused Kind argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165833 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a transposed algorithm for handleMove().Jakob Stoklund Olesen2012-10-121-427/+213
| | | | | | | | | | | | | Completely update one interval at a time instead of collecting live range fragments to be updated. This avoids building data structures, except for a single SmallPtrSet of updated intervals. Also share code between handleMove() and handleMoveIntoBundle(). Add support for moving dead defs across other live values in the interval. The MI scheduler can do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165824 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix coalescing with IMPLICIT_DEF values.Jakob Stoklund Olesen2012-10-121-21/+54
| | | | | | | | | | | | | | | | PHIElimination inserts IMPLICIT_DEF instructions to guarantee that all PHI predecessors have a live-out value. These IMPLICIT_DEF values are not considered to be real interference when coalescing virtual registers: %vreg1 = IMPLICIT_DEF %vreg2 = MOV32r0 When joining %vreg1 and %vreg2, the IMPLICIT_DEF instruction and its value number should simply be erased since the %vreg2 value number now provides a live-out value for the PHI predecesor block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165813 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCASTUlrich Weigand2012-10-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | On PowerPC, a bitcast of <16 x i8> to i128 may run through a code path in ExpandRes_BITCAST that attempts to do an intermediate bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts of the resulting i128 by pairing up two of those i32 vector elements each. The code already recognizes that on a big-endian system, the first two vector elements form the Hi part, and the final two vector elements form the Lo part (vice-versa from the little-endian situation). However, we also need to take endianness into account when forming each of those separate pairs: on a big-endian system, vector element 0 is the *high* part of the pair making up the Hi part of the result, and vector element 1 is the low part of the pair. The code currently always uses vector element 0 as the low part and vector element 1 as the high part, as is appropriate for little-endian platforms only. This patch fixes this by swapping the vector elements as they are paired up as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165802 91177308-0d34-0410-b5e6-96231b3b80d8
* Add powerpc-ibm-aix to Triple. Patch by Kai.Duncan Sands2012-10-121-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165792 91177308-0d34-0410-b5e6-96231b3b80d8
* Indenting.Eric Christopher2012-10-121-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165785 91177308-0d34-0410-b5e6-96231b3b80d8
* fix warningSebastian Pop2012-10-121-6/+6
| | | | | | | | | | | DependenceAnalysis.cpp:1164:32: warning: implicit truncation from 'int' to bitfield changes value from -5 to 3 [-Wconstant-conversion] Result.DV[Level].Direction &= ~Dependence::DVEntry::GT; ^ ~~~~~~~~~~~~~~~~~~~~~~~~ Patch from Preston Briggs <preston.briggs@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165784 91177308-0d34-0410-b5e6-96231b3b80d8
* Div, Rem int/unsigned int Reed Kotler2012-10-122-8/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165783 91177308-0d34-0410-b5e6-96231b3b80d8
* Legalizer optimize a pair of div / mod to a call to divrem libcall if they areEvan Cheng2012-10-121-0/+2
| | | | | | | | | | | not legal. However, it should use a div instruction + mul + sub if divide is legal. The rem legalization code was missing a check and incorrectly uses a divrem libcall even when div is legal. rdar://12481395 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165778 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary classof()'sSean Silva2012-10-115-20/+0
| | | | | | | isa<> et al. automatically infer when the cast is an upcast (including a self-cast), so these are no longer necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove buggy classof().Sean Silva2012-10-111-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This classof() is effectively saying that a MachineCodeEmitter "is-a" JITEmitter, but JITEmitter is in fact a descendant of MachineCodeEmitter, so this is not semantically correct. Consequently, none of the assertions that rely on these classof() actualy check anything. Remove the RTTI (which didn't actually check anything) and use static_cast<> instead. Post-Mortem Bug Analysis ======================== Cause of the bug ---------------- r55022 appears to be the source of the classof() and assertions removed by this commit. It aimed at removing some dynamic_cast<> that were solely in the assertions. A typical diff hunk from that commit looked like: - assert(dynamic_cast<JITEmitter*>(MCE) && "Unexpected MCE?"); - JITEmitter *JE = static_cast<JITEmitter*>(getCodeEmitter()); + assert(isa<JITEmitter>(MCE) && "Unexpected MCE?"); + JITEmitter *JE = cast<JITEmitter>(getCodeEmitter()); Hence, the source of the bug then seems to be an attempt to replace dynamic_cast<> with LLVM-style RTTI without properly setting up the class hierarchy for LLVM-style RTTI. The bug therefore appears to be simply a "thinko". What initially indicated the presence of the bug ------------------------------------------------ After implementing automatic upcasting for isa<>, classof() functions of the form static bool classof(const Foo *) { return true; } were removed, since they only serve the purpose of optimizing statically-OK upcasts. A subsequent recompilation triggered a build failure on the isa<> tests within the removed asserts, since the automatic upcasting (correctly) failed to substitute this classof(). Key to pinning down the root cause of the bug --------------------------------------------- After being alerted to the presence of the bug, some thought about the semantics which were being asserted by the buggy classof() revealed that it was incorrect. How the bug could have been prevented ------------------------------------- This bug could have been prevented by better documentation for how to set up LLVM-style RTTI. This should be solved by the recently added documentation HowToSetUpLLVMStyleRTTI. However, this bug suggests that the documentation should clearly explain the contract that classof() must fulfill. The HowToSetUpLLVMStyleRTTI already explains this contract, but it is a little tucked away. A future patch will expand that explanation and make it more prominent. There does not appear to be a simple way to have the compiler prevent this bug, since fundamentally it boiled down to a spurious classof() where the programmer made an erroneous statement about the conversion. This suggests that perhaps the interface to LLVM-style RTTI of classof() is not the best. There is already some evidence for this, since in a number of places Clang has classof() forward to classofKind(Kind K) which evaluates the cast in terms of just the Kind. This could probably be generalized to simply a `static const Kind MyKind;` field in leaf classes and `static const Kind firstMyKind, lastMyKind;` for non-leaf classes, and have the rest of the work be done inside Casting.h, assuming that the Kind enum is laid out in a preorder traversal of the inheritance tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165764 91177308-0d34-0410-b5e6-96231b3b80d8
* PGO: create metadata for switch only if it has more than one targets.Manman Ren2012-10-111-1/+1
| | | | | | | | When all cases of a switch statement are dead, the weights vector only has one element, and we will get an ssertion failure when calling createBranchWeights. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165759 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some typos 165739, spotted by Duncan.Jan Wen Voung2012-10-112-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165753 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 165732 for further review.Micah Villmow2012-10-1135-142/+92
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
* Change encoding of instruction operands in bitcode binaries to be relativeJan Wen Voung2012-10-113-90/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | to the instruction position. The old encoding would give an absolute ID which counts up within a function, and only resets at the next function. I.e., Instead of having: ... = icmp eq i32 n-1, n-2 br i1 ..., label %bb1, label %bb2 it will now be roughly: ... = icmp eq i32 1, 2 br i1 1, label %bb1, label %bb2 This makes it so that ids remain relatively small and can be encoded in fewer bits. With this encoding, forward reference operands will be given negative-valued IDs. Use signed VBRs for the most common case of forward references, which is phi instructions. To retain backward compatibility we bump the bitcode version from 0 to 1 to distinguish between the different encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165739 91177308-0d34-0410-b5e6-96231b3b80d8
* Add in the first iteration of support for llvm/clang/lldb to allow variable ↵Micah Villmow2012-10-1135-92/+142
| | | | | | per address space pointer sizes to be optimized correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass an explicit operand number to addLiveIns.Jakob Stoklund Olesen2012-10-112-8/+8
| | | | | | | | | Not all instructions define a virtual register in their first operand. Specifically, INLINEASM has a different format. <rdar://problem/12472811> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165721 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch addresses PR13947.Bill Schmidt2012-10-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | | For function calls on the 64-bit PowerPC SVR4 target, each parameter is mapped to as many doublewords in the parameter save area as necessary to hold the parameter. The first 13 non-varargs floating-point values are passed in registers; any additional floating-point parameters are passed in the parameter save area. A single-precision floating-point parameter (32 bits) must be mapped to the second (rightmost, low-order) word of its assigned doubleword slot. Currently LLVM violates this ABI requirement by mapping such a parameter to the first (leftmost, high-order) word of its assigned doubleword slot. This is internally self-consistent but will not interoperate correctly with libraries compiled with an ABI-compliant compiler. This patch corrects the problem by adjusting the parameter addressing on both sides of the calling convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165714 91177308-0d34-0410-b5e6-96231b3b80d8
* Expose move to/from coprocessor instructions in MIPS64 mode.David Chisnall2012-10-111-0/+30
| | | | | | | | | | | | | Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
* dependence analysisSebastian Pop2012-10-113-0/+3783
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Preston Briggs <preston.briggs@gmail.com>. This is an updated version of the dependence-analysis patch, including an MIV test based on Banerjee's inequalities. It's a fairly complete implementation of the paper Practical Dependence Testing Gina Goff, Ken Kennedy, and Chau-Wen Tseng PLDI 1991 It cannot yet propagate constraints between coupled RDIV subscripts (discussed in Section 5.3.2 of the paper). It's organized as a FunctionPass with a single entry point that supports testing for dependence between two instructions in a function. If there's no dependence, it returns null. If there's a dependence, it returns a pointer to a Dependence which can be queried about details (what kind of dependence, is it loop independent, direction and distance vector entries, etc). I haven't included every imaginable feature, but there's a good selection that should be adequate for supporting many loop transformations. Of course, it can be extended as necessary. Included in the patch file are many test cases, commented with C code showing the loops and array references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165708 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow the same routine to add target float expansion hookMichael Liao2012-10-111-26/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165707 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Handle "transient" non-instructions.Andrew Trick2012-10-112-17/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash when !tbaa.struct contents is invalid.Nick Lewycky2012-10-111-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165693 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."NAKAMURA Takumi2012-10-111-40/+0
| | | | | | It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165692 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the LLVM context to this c'tor. It will be needed in the future.Bill Wendling2012-10-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165687 91177308-0d34-0410-b5e6-96231b3b80d8
* Support a common idiom on how to build an Attributes class with a single ↵Bill Wendling2012-10-111-0/+3
| | | | | | attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165686 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash if a .ll file contains a forward-reference that looks like a globalNick Lewycky2012-10-111-0/+3
| | | | | | | | | | value but later turns out to be a function. Unfortunately, we can't fold tests into a single file because we only get one error out of llvm-as. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165680 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng2012-10-111-5/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165677 91177308-0d34-0410-b5e6-96231b3b80d8
* Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng2012-10-101-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165673 91177308-0d34-0410-b5e6-96231b3b80d8
* Add getters for the MIPS TargetTransform classesNadav Rotem2012-10-101-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165670 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused member variable introduced in r165665.David Blaikie2012-10-101-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165669 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem2012-10-1031-102/+301
| | | | | | information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch by Shuxin Yang <shuxin.llvm@gmail.com>.Nadav Rotem2012-10-101-0/+40
| | | | | | | | | | | | | | | | | | | | | Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165661 91177308-0d34-0410-b5e6-96231b3b80d8
* When generating spill and reload code for vector registers on PowerPC,Bill Schmidt2012-10-101-6/+12
| | | | | | | | | | | | | the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
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