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* CVP: If we have a PHI with an incoming select, try to skip the select.Benjamin Kramer2013-02-241-5/+24
| | | | | | | | | | This is a common pattern with dyn_cast and similar constructs, when the PHI no longer depends on the select it can often be turned into a simpler construct or even get hoisted out of the loop. PR15340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175995 91177308-0d34-0410-b5e6-96231b3b80d8
* TypoFrancois Pichet2013-02-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175991 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r169638 because it broke Mesa llvmpipe tests.Nadav Rotem2013-02-241-6/+1
| | | | | | | | Fix PR15239. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175985 91177308-0d34-0410-b5e6-96231b3b80d8
* Make psuedo FEXT_T8I816_ins a custom inserter. It should be expandedReed Kotler2013-02-244-22/+34
| | | | | | | | as early as possible; which means during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175984 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a use of an otherwise unused variable to remove a warning in non-AssertsCameron Zwarich2013-02-241-0/+1
| | | | | | builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175981 91177308-0d34-0410-b5e6-96231b3b80d8
* TwoAddressInstructionPass::tryInstructionTransform() only potentially returnsCameron Zwarich2013-02-241-5/+4
| | | | | | | true when shouldOnlyCommute is false, so we can remove code that checks otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175980 91177308-0d34-0410-b5e6-96231b3b80d8
* TwoAddrInstructionPass::tryInstructionTransform() has a case where it callsCameron Zwarich2013-02-241-5/+10
| | | | | | | | | | | | | | | | itself recursively with a new instruction that has not been finalized, in order to determine whether to keep the instruction. On 'make check' and test-suite the only cases where the recursive invocation made any transformations were simple instruction commutations, so I am restricting the recursive invocation to do only this. The other cases wouldn't work correctly when updating LiveIntervals, since the new instructions don't have slot indices and LiveIntervals hasn't yet been updated. If the other transformations were actually triggering in any test case it would be possible to support it with a lot of effort, but since they don't it's not worth it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175979 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new base instruction def for cmpi, cmp, slt and sltu so that def/usesReed Kotler2013-02-231-5/+10
| | | | | | | | proper. Fixed this already a few days ago for slti. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175975 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetInstrInfo::commuteInstruction() doesn't actually return a new instructionCameron Zwarich2013-02-231-13/+3
| | | | | | | unless it was requested to with an optional parameter that defaults to false, so we don't need to handle that case in TwoAddressInstructionPass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175974 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Disable cmov-memory patterns on subtargets without cmov.Benjamin Kramer2013-02-231-6/+8
| | | | | | Fixes PR15115. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175962 91177308-0d34-0410-b5e6-96231b3b80d8
* Make some fixes for LiveInterval repair with debug info. Debug valueCameron Zwarich2013-02-232-2/+6
| | | | | | MachineInstrs don't have a slot index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175961 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug with the LiveIntervals updating in the two-address pass found byCameron Zwarich2013-02-231-1/+1
| | | | | | running ASCI_Purple/SMG2000 in the test-suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175957 91177308-0d34-0410-b5e6-96231b3b80d8
* Make TwoAddressInstructionPass::sink3AddrInstruction() LiveIntervals-aware.Cameron Zwarich2013-02-231-15/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175956 91177308-0d34-0410-b5e6-96231b3b80d8
* Make rescheduleMIBelowKill() and rescheduleKillAboveMI() LiveIntervals-aware inCameron Zwarich2013-02-231-30/+85
| | | | | | | | TwoAddressInstructionPass. The code in rescheduleMIBelowKill() is a bit tricky, since multiple instructions need to be moved down, one-at-a-time, in reverse order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175955 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand pseudos/macros for Selt. This is the last of the complexReed Kotler2013-02-233-0/+82
| | | | | | | | macros.The rest is some small misc. stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-233-0/+28
| | | | | | | | Handle an implied 'sp' operand. rdar://11466783 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a careless mistake.Michael Gottesman2013-02-231-1/+1
| | | | | | rdar://13273675. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175939 91177308-0d34-0410-b5e6-96231b3b80d8
* Use getSplitDebugFilename when constructing the skeleton cu andEric Christopher2013-02-221-4/+2
| | | | | | update testcase accordingly to give the correct name to the cu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175934 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a field to the compile unit of where we plan on splitting outEric Christopher2013-02-221-2/+3
| | | | | | | the debug info for -gsplit-dwarf so we can encode that location in the skeleton cu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175933 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TODO and explain when we can get rid of the isMain field.Eric Christopher2013-02-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175932 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG compile time improvement.Nadav Rotem2013-02-221-0/+19
| | | | | | | | | | One of the phases of SelectionDAG is LegalizeVectors. We don't need to sort the DAG and copy nodes around if there are no vector ops. Speeds up the compilation time of SelectionDAG on a big scalar workload by ~8%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175929 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Emit call16 operator instead of got_disp. The former allows lazy binding.Akira Hatanaka2013-02-221-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175920 91177308-0d34-0410-b5e6-96231b3b80d8
* x86_64: designate most general purpose and SSE registers as callee save ↵Peter Collingbourne2013-02-222-21/+28
| | | | | | under coldcc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175911 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for sign extension of i1 to i32.Michel Danzer2013-02-221-0/+5
| | | | | | | | | | 16 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175887 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for logical or of i1 values.Michel Danzer2013-02-221-0/+4
| | | | | | | | | | 24 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175886 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for fceil.Michel Danzer2013-02-221-1/+3
| | | | | | | | | | 9 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175885 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-221-2/+1
| | | | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
* Use references to attribute groups on the call/invoke instructions.Bill Wendling2013-02-221-9/+11
| | | | | | | | Listing all of the attributes for the callee of a call/invoke instruction is way too much and makes the IR unreadable. Use references to attributes instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175877 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refersReed Kotler2013-02-222-8/+8
| | | | | | | | to the immediate operand of sli or cmp function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175865 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand mips16 SelT form pseudso/macros.Reed Kotler2013-02-223-0/+81
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175862 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix isa<> check which could never be true.Pete Cooper2013-02-221-1/+1
| | | | | | | | | | | | It was incorrectly checking a Function* being an IntrinsicInst* which isn't possible. It should always have been checking the CallInst* instead. Added test case for x86 which ensures we only get one constant load. It was 2 before this change. rdar://problem/13267920 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175853 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove code copied from GenRegisterInfo.inc.Andrew Trick2013-02-222-57/+0
| | | | | | | | There's no apparent reason this code was copied from generated source into a .cpp. It sets a bad example for those working on other targets and trying to understand the register info API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175849 91177308-0d34-0410-b5e6-96231b3b80d8
* Code cleanup: pass Offset by pointer to parseInstruction to more explicitlyEli Bendersky2013-02-221-29/+33
| | | | | | | | | convey that it's a INOUT argument. Also, if parsing of entry instructions fails, don't push the entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175847 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove warning about default covering no cases.Bill Wendling2013-02-221-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175846 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bitmask for NoBuiltin. This should *not* be used.Bill Wendling2013-02-221-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175843 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the NoBuiltin attribute.Bill Wendling2013-02-228-10/+59
| | | | | | | | | The 'nobuiltin' attribute is applied to call sites to indicate that LLVM should not treat the callee function as a built-in function. I.e., it shouldn't try to replace that function with different code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175835 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop relying on physical register kill flags in isKilled() in the two-addressCameron Zwarich2013-02-211-3/+10
| | | | | | | | | | | | | | pass. One of the callers of isKilled() can cope with overapproximation of kills and the other can't, so I added a flag to indicate this. In theory this could pessimize code slightly, but in practice most physical register uses are kills, and most important kills of physical registers are the only uses of that register prior to register allocation, so we can recognize them as kills even without kill flags. This is relevant because LiveIntervals gets rid of all kill flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175821 91177308-0d34-0410-b5e6-96231b3b80d8
* Previously, parsing capability of the .debug_frame section was addedEli Bendersky2013-02-212-6/+171
| | | | | | | | | | | | | | | | | to lib/DebugInfo, with dumping in llvm-dwarfdump. This patch adds initial ability to parse and dump CFA instructions contained in entries. To keep it manageable, the patch omits some more advanced capabilities (accounted in TODOs): * Parsing of instructions with BLOCK arguments (expression lists) * Dumping of actual instruction arguments (currently only names are dumped). This is quite tricky since the dumper has to effectively "interpret" the instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175820 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow GlobalValues to vectorize with AliasAnalysisRenato Golin2013-02-211-35/+154
| | | | | | | | | | | | | | | | | | | | | Storing the load/store instructions with the values and inspect them using Alias Analysis to make sure they don't alias, since the GEP pointer operand doesn't take the offset into account. Trying hard to not add any extra cost to loads and stores that don't overlap on global values, AA is *only* calculated if all of the previous attempts failed. Using biggest vector register size as the stride for the vectorization access, as we're being conservative and the cost model (which calculates the real vectorization factor) is only run after the legalization phase. We might re-think this relationship in the future, but for now, I'd rather be safe than sorry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175818 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply r175688, with the changes suggested by Jakob in PR15320.Lang Hames2013-02-211-24/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175809 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code and whitespace.Chad Rosier2013-02-211-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175804 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-2154-572/+543
| | | | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assert on empty attributes.Bill Wendling2013-02-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175785 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
* Make RAFast::UsedInInstr indexed by register units.Jakob Stoklund Olesen2013-02-211-22/+30
| | | | | | | | | | This fixes some problems with too conservative checking where we were marking all aliases of a register as used, and then also checking all aliases when allocating a register. <rdar://problem/13249625> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175782 91177308-0d34-0410-b5e6-96231b3b80d8
* Radar numbers don't belong in source code.Evan Cheng2013-02-213-4/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175775 91177308-0d34-0410-b5e6-96231b3b80d8
* Trivial cleanupBill Schmidt2013-02-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175771 91177308-0d34-0410-b5e6-96231b3b80d8
* Large code model support for PowerPC.Bill Schmidt2013-02-215-15/+20
| | | | | | | | | | | | Large code model is identical to medium code model except that the addis/addi sequence for "local" accesses is never used. All accesses use the addis/ld sequence. The coding changes are straightforward; most of the patch is taken up with creating variants of the medium model tests for large model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r175688 - It broke a test case (see PR15320).Lang Hames2013-02-211-13/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175765 91177308-0d34-0410-b5e6-96231b3b80d8
* getX86SubSuperRegister has a special mode with High=true for i64 whichEli Bendersky2013-02-211-17/+9
| | | | | | | | | | | | exists solely to enable it to call itself for i8 with some registers. The proposed patch simplifies the function somewhat to make the High bit only meaningful for the i8 mode, which makes sense. No functional difference (getX86SubSuperRegister is not getting called from anywhere outside with i64 and High=true). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175762 91177308-0d34-0410-b5e6-96231b3b80d8
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