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* [SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford2013-09-306-14/+38
| | | | | | | | | | The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191660 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rename subregs and add subreg_h32Richard Sandiford2013-09-309-60/+61
| | | | | | | | | | | | | | Use subreg_hNN and subreg_lNN for the high and low NN bits of a register. List the low registers first, so that subreg_l32 also means the low 32 bits of a 128-bit register. Floats are stored in the upper 32 bits of a 64-bit register, so they should use subreg_h32 rather than subreg_l32. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191659 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add change missing from previous commitRichard Sandiford2013-09-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191656 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rename 32-bit GPR registersRichard Sandiford2013-09-306-20/+20
| | | | | | | | | I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
* Various x86 disassembler fixes.Craig Topper2013-09-303-47/+12
| | | | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191649 91177308-0d34-0410-b5e6-96231b3b80d8
* ObjectSizeOffsetEvaluator: Don't run into infinite recursion if we have a ↵Benjamin Kramer2013-09-291-5/+7
| | | | | | | | cyclic GEP. Those can occur in dead code. PR17402. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191644 91177308-0d34-0410-b5e6-96231b3b80d8
* Deallocate type units when destroying a DWARFContext.Benjamin Kramer2013-09-291-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191637 91177308-0d34-0410-b5e6-96231b3b80d8
* Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.Benjamin Kramer2013-09-291-2/+10
| | | | | | | SDNode destructors are never called. As an optimization use AtomicSDNode's internal storage if we have a small number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191636 91177308-0d34-0410-b5e6-96231b3b80d8
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-292-14/+8
| | | | | | cases from switch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191632 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments for XOPA map introduced with TBM instructions.aCraig Topper2013-09-292-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191630 91177308-0d34-0410-b5e6-96231b3b80d8
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-2811-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-286-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191610 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Silence unused variable warning on release buildsTom Stellard2013-09-281-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191604 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-283-44/+40
| | | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-282-17/+49
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191602 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-285-94/+91
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Clean up LegalizeSetCCCondCode() functionTom Stellard2013-09-281-26/+51
| | | | | | | | | | | | | | Interpreting the results of this function is not very intuitive, so I cleaned it up to make it more clear whether or not a SETCC op was legalized and how it was legalized (either by swapping LHS and RHS or replacing with AND/OR). This patch does change functionality in the LHS and RHS swapping case, but unfortunately there are no in-tree tests for this. However, this patch is a prerequisite for R600 to take advantage of the LHS and RHS swapping, so tests will be added in subsequent commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191600 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsMachineFunction.cpp: Add missing #include <raw_ostream.h>NAKAMURA Takumi2013-09-281-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191597 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoMatt Arsenault2013-09-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191595 91177308-0d34-0410-b5e6-96231b3b80d8
* AutoUpgrade: upgrade from scalar TBAA format to struct-path aware TBAA format.Manman Ren2013-09-285-0/+44
| | | | | | | | We treat TBAA tags as struct-path aware TBAA format when the first operand is a MDNode and the tag has 3 or more operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191593 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted outAkira Hatanaka2013-09-284-19/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: try to fix the dragonegg bots.Manman Ren2013-09-271-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191585 91177308-0d34-0410-b5e6-96231b3b80d8
* Unify conditionals and reformat.Eric Christopher2013-09-271-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191582 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor code simplificationMatt Arsenault2013-09-271-11/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191579 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define a derived class of PseudoSourceValue that represents a GOT entryAkira Hatanaka2013-09-272-0/+106
| | | | | | | | | resolved by lazy-binding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191578 91177308-0d34-0410-b5e6-96231b3b80d8
* Use right pointer type in DebugIRMatt Arsenault2013-09-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191576 91177308-0d34-0410-b5e6-96231b3b80d8
* Use type helper functionsMatt Arsenault2013-09-273-6/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191574 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework conditional for printing out pub sections.Eric Christopher2013-09-271-7/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191571 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Refactor the StackProtector pass from a single .cpp file ↵Josh Magee2013-09-271-70/+1
| | | | | | | | | | | | | | | into StackProtector.h and StackProtector.cpp. No functionality change. Future patches will add analysis which will be used in other passes (PEI, StackSlot). The end goal is to support ssp-strong stack layout rules. WIP. Differential Revision: http://llvm-reviews.chandlerc.com/D1521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191570 91177308-0d34-0410-b5e6-96231b3b80d8
* Object/COFF: Rename getXXX{Begin,End} -> xxx_{begin,end}.Rui Ueyama2013-09-272-10/+10
| | | | | | | It is mentioned in the LLVM coding standard that _begin() and _end() suffixes should be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191569 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SLPVectorizer using wrong address space for load/storeMatt Arsenault2013-09-271-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191564 91177308-0d34-0410-b5e6-96231b3b80d8
* SourceMgr diagnotics printing: fix a bug where printing a fixit for a sourceDmitri Gribenko2013-09-271-1/+1
| | | | | | | | range that includes a tab character will cause out-of-bounds access to the fixit string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191563 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SourceMgr::PrintMessage() testable and add unit testsDmitri Gribenko2013-09-271-3/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191558 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-submit r191472 with a fix for big endian.Rui Ueyama2013-09-271-30/+166
| | | | | | llvm-objdump: Dump COFF import table if -private-headers option is given. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191557 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Only foldSelectICmpAndOr for integer typesJustin Bogner2013-09-271-1/+1
| | | | | | | | | | Currently foldSelectICmpAndOr asserts if the "or" involves a vector containing several of the same power of two. We can easily avoid this by only performing the fold on integer types, like foldSelectICmpAnd does. Fixes <rdar://problem/15012516> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191552 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rewrite MipsTargetLowering::getAddr functions as template functions.Akira Hatanaka2013-09-273-81/+135
| | | | | | | | | No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-275-0/+89
| | | | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: handle scalar TBAA format and struct-path aware TBAA format.Manman Ren2013-09-271-10/+81
| | | | | | | | | | | | | | | | | Remove the command line argument "struct-path-tbaa" since we should not depend on command line argument to decide which format the IR file is using. Instead, we check the first operand of the tbaa tag node, if it is a MDNode, we treat it as struct-path aware TBAA format, otherwise, we treat it as scalar TBAA format. When clang starts to use struct-path aware TBAA format no matter whether struct-path-tbaa is no, and we can auto-upgrade existing bc files, the support for scalar TBAA format can be dropped. Existing testing cases are updated to use the struct-path aware TBAA format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191538 91177308-0d34-0410-b5e6-96231b3b80d8
* Transforms: Use getFirstNonPHI to set the insertion point for PHIsJustin Bogner2013-09-272-2/+2
| | | | | | | | | | We were previously using getFirstInsertionPt to insert PHI instructions when vectorizing, but getFirstInsertionPt also skips past landingpads, causing this to generate invalid IR. We can avoid this issue by using getFirstNonPHI instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191526 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Rein back the use of block operationsRichard Sandiford2013-09-272-22/+28
| | | | | | | | | | | | | | | The backend tries to use block operations like MVC, NC, OC and XC for simple scalar operations. For correctness reasons, it rejects any case in which the regions might partially overlap. However, for performance reasons, it should also reject cases where the regions might be equal, since the instruction might then not use the fast path. This fixes a performance regression seen in bzip2. We may want to limit the optimisation even more in future, or even remove it entirely, but I'll try with this for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191525 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Improve handling of PC-relative addressesRichard Sandiford2013-09-275-59/+92
| | | | | | | | | | | | | | | The backend previously folded offsets into PC-relative addresses whereever possible. That's the right thing to do when the address can be used directly in a PC-relative memory reference (using things like LRL). But if we have a register-based memory reference and need to load the PC-relative address separately, it's better to use an anchor point that could be shared with other accesses to the same area of the variable. Fixes a FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191524 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert.d intrinsic.Daniel Sanders2013-09-271-14/+3
| | | | | | | | | This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191521 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Teach assembler to enforce constraints for ARM LDRD destination ↵Tilmann Scheller2013-09-271-1/+10
| | | | | | | | | | | | | | | | | | | | | register operands. As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented fill.d intrinsic.Daniel Sanders2013-09-271-3/+5
| | | | | | | | | This intrinsic is lowered into an equivalent BUILD_VECTOR which is further lowered into a sequence of insert.w's on MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented copy_[us].d intrinsic.Daniel Sanders2013-09-272-0/+21
| | | | | | | | | This intrinsic is lowered into equivalent copy_s.w instructions during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Rename arguments to MSA_INSERT_DESC_BASE to better match their ↵Daniel Sanders2013-09-271-6/+6
| | | | | | | | | | expected values. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191517 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.Daniel Sanders2013-09-273-0/+85
| | | | | | | | | For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191515 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64Daniel Sanders2013-09-273-4/+104
| | | | | | | | | For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for MSA registers to copyPhysRegDaniel Sanders2013-09-271-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191512 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-279-8/+93
| | | | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
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