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* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-171-3/+2
| | | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
* When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling2010-11-011-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
* More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when theBill Wendling2010-11-011-4/+3
| | | | | | | peephole optimizer is disabled. That's not good at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable because peephole is disabled.Bill Wendling2010-11-011-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM instructions that are both predicated and set the condition codesBob Wilson2010-10-151-0/+47
| | | | | | | | | | | have been printed with the "S" modifier after the predicate. With ARM's unified syntax, they are supposed to go in the other order. We fixed this for Thumb when we switched to unified syntax but missed changing it for ARM. Apparently we don't generate these instructions often because no one noticed until now. Thanks to Bill Wendling for the testcase! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
* do not compare actual branch labels; this may fix ↵Gabor Greif2010-09-291-3/+3
| | | | | | llvm-gcc-x86_64-darwin10-cross-mingw32 buildbot too git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115034 91177308-0d34-0410-b5e6-96231b3b80d8
* improve heuristics to find the 'and' corresponding to 'tst' to also catch ↵Gabor Greif2010-09-291-8/+12
| | | | | | | | opportunities on thumb2 added some doxygen on the way git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115033 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable code placement optimization pass for ARM.Evan Cheng2010-09-241-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply Gabor's 113839, 113840, and 113876 with a fix for a problemBob Wilson2010-09-151-2/+1
| | | | | | | | | encountered while building llvm-gcc for arm. This is probably the same issue that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator, not a plain MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
* the darwin9-powerpc buildbot keeps consistently crashing,Gabor Greif2010-09-151-1/+2
| | | | | | | | | | backing out following to get it back to green, so I can investigate in peace: svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
* forgot the testcase change for r113839Gabor Greif2010-09-141-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113840 91177308-0d34-0410-b5e6-96231b3b80d8
* test for and-tst peephole optimizationGabor Greif2010-09-141-0/+58
documents the status-quo with its opportunities git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113838 91177308-0d34-0410-b5e6-96231b3b80d8
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