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* Update to LLVM 3.5a.Stephen Hines2014-04-241-4/+4
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier ↵Stephen Lin2013-07-131-5/+5
| | | | | | | | | | | debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some register allocation order dependencies.Jakob Stoklund Olesen2013-01-191-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172874 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LLVM support for Swift.Bob Wilson2012-09-291-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-191-1/+1
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-281-1/+1
| | | | | | to fail. Ugh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
* - Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng2010-10-281-1/+1
| | | | | | | | | | | - For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARM scheduling default to list-hybrid if the target supports floating ↵Evan Cheng2010-05-211-1/+1
| | | | | | point instructions (and is not using soft float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-251-2/+1
| | | | | | Re-commit. This time complete with testsuite updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert ARM tests to FileCheck for PR5307.Edward O'Callaghan2009-11-221-5/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89593 91177308-0d34-0410-b5e6-96231b3b80d8
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-011-2/+2
| | | | | | -arm-use-neon-fp to override the default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-091-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
* Make NEON single-precision FP support the default for cortex-a8 (again).David Goodwin2009-08-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ↵David Goodwin2009-08-041-0/+10
to enable. Added patterns for some binary FP operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
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