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* Add some missing isel predicates on def : pat patterns to avoid generating ↵Evan Cheng2010-11-121-9/+9
| | | | | | VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-8/+8
| | | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
* Try again to disable critical edge splitting in CodeGenPrepare.Jakob Stoklund Olesen2010-09-301-2/+2
| | | | | | The bug that broke i386 linux has been fixed in r115191. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115204 91177308-0d34-0410-b5e6-96231b3b80d8
* Part one of switching to using a more sane heuristic for determining ↵Owen Anderson2010-09-281-2/+1
| | | | | | | | | | | | if-conversion profitability. Rather than having arbitrary cutoffs, actually try to cost model the conversion. For now, the constants are tuned to more or less match our existing behavior, but these will be changed to reflect realistic values as this work proceeds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Disable codegen prepare critical edge splitting. Machine instruction ↵Jakob Stoklund Olesen2010-09-271-3/+3
| | | | | | | | | | | | | | | passes now" This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost. It seems there is a downstream bug that is exposed by -cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back in. Note that the changes to tailcallfp2.ll are not reverted. They were good are required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114859 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable codegen prepare critical edge splitting. Machine instruction passes nowEvan Cheng2010-09-231-3/+3
| | | | | | | break critical edges on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114633 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that register allocation properly considers reserved regs, simplify theJim Grosbach2010-09-021-1/+1
| | | | | | | ARM register class allocation order functions to take advantage of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
* The optimize comparisons pass removes the "cmp" instruction this is checking ↵Bill Wendling2010-08-101-1/+0
| | | | | | for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110739 91177308-0d34-0410-b5e6-96231b3b80d8
* - Allow target to specify when is register pressure "too high". In most cases,Evan Cheng2010-07-231-8/+8
| | | | | | | | | | | | | | it's too late to start backing off aggressive latency scheduling when most of the registers are in use so the threshold should be a bit tighter. - Correctly handle live out's and extract_subreg etc. - Enable register pressure aware scheduling by default for hybrid scheduler. For ARM, this is almost always a win on # of instructions. It's runtime neutral for most of the tests. But for some kernels with high register pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by 54 and sped up by 20%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
* More register pressure aware scheduling work.Evan Cheng2010-07-211-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
* We are missing opportunites to use ldm. Take code like this:Bill Wendling2010-06-231-3/+5
| | | | | | | | | | | | | | | void t(int *cp0, int *cp1, int *dp, int fmd) { int c0, c1, d0, d1, d2, d3; c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); /* ... */ } It code gens into something pretty bad. But with this change (analogous to the X86 back-end), it will use ldm and generate few instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola2010-06-171-2/+2
| | | | | | matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some latency computation bugs: if the use is not a machine opcode do not ↵Evan Cheng2010-05-281-10/+10
| | | | | | just return zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
* When canonicalizing icmp operand order to put the loop invariantDan Gohman2010-05-201-0/+256
| | | | | | | | | | | | | operand on the left, the interesting operand is on the right. This fixes a bug where LSR was failing to recognize ICmpZero uses, which led it to be unable to reverse the induction variable in the attached testcase. Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test is extremely fragile and hard to meaningfully update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LSR how to cope better with unrolled loops on targets whereDan Gohman2010-05-191-0/+386
the addressing modes don't make this trivially easy. This allows it to avoid falling into the less precise heuristics in more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104186 91177308-0d34-0410-b5e6-96231b3b80d8