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* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-1/+1
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-311-33/+33
| | | | | | | | | | | | Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.Justin Holewinski2013-03-301-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds a new NVPTX back-end to LLVM which supports code generation ↵Justin Holewinski2012-05-041-0/+284
for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8