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	Commit message (Collapse)	Author	Age	Files	Lines
*	Update aosp/master llvm for rebase to r233350	Pirama Arumuga Nainar	2015-04-09	1	-2/+2
\| \| \| \|	Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
*	Don't reserve R2 on Darwin/PPC	Hal Finkel	2013-03-12	1	-2/+2
\| \| \| \| \| \| \| \| \| \| \|	Now that only the register-scavenger version of the CR spilling code remains, we no longer need the Darwin R2 hack. Darwin can use R0 as a spare register in any case where the System V ABI uses it (R0 is special architecturally, and so is reserved under all common ABIs). A few test cases needed to be updated to reflect the register-allocation changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176868 91177308-0d34-0410-b5e6-96231b3b80d8
*	Enable ILP scheduling for all nodes by default on PPC.	Hal Finkel	2012-06-10	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Over the entire test-suite, this has an insignificantly negative average performance impact, but reduces some of the worst slowdowns from the anti-dep. change (r158294). Largest speedups: SingleSource/Benchmarks/Stanford/Quicksort - 28% SingleSource/Benchmarks/Stanford/Towers - 24% SingleSource/Benchmarks/Shootout-C++/matrix - 23% MultiSource/Benchmarks/SciMark2-C/scimark2 - 19% MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15% (matrix and automotive-bitcount were both in the top-5 slowdown list from the anti-dep. change) Largest slowdowns: MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28% MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26% MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21% SingleSource/Benchmarks/CoyoteBench/lpbench - 20% MultiSource/Applications/d/make_dparser - 16% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296 91177308-0d34-0410-b5e6-96231b3b80d8
*	Fix some latency computation bugs: if the use is not a machine opcode do not ↵	Evan Cheng	2010-05-28	1	-2/+2
\| \| \| \| \| \|	just return zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
*	Make g5 target explicit; scheduling affects register choice.	Dale Johannesen	2010-02-16	1	-1/+1
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96413 91177308-0d34-0410-b5e6-96231b3b80d8
*	Adjust register numbers in tests to compensate for the	Dale Johannesen	2010-02-16	1	-2/+2
\| \| \| \| \| \| \| \|	new lack of R2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96407 91177308-0d34-0410-b5e6-96231b3b80d8
*	Eliminate more uses of llvm-as and llvm-dis.	Dan Gohman	2009-09-09	1	-1/+1
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
*	Alter 79292 to produce output that actually assembles.	Dale Johannesen	2009-08-26	1	-1/+4
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80119 91177308-0d34-0410-b5e6-96231b3b80d8
*	PowerPC inline asm was emitting two output operands	Dale Johannesen	2009-08-18	1	-0/+22
	for a single "m" constraint; this is wrong because the opcode of a load or store would have to change in parallel. This patch makes it always compute addresses into a register, which is correct but not as efficient as possible. 7144566. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8