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	Commit message (Collapse)	Author	Age	Files	Lines
*	Update aosp/master llvm for rebase to r233350	Pirama Arumuga Nainar	2015-04-09	1	-5/+5
\| \| \| \|	Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
*	Fix cpu on test CodeGen/PowerPC/ctrloop-fp64.ll	Hal Finkel	2013-05-16	1	-1/+1
\| \| \| \| \| \|	We need ppc instead of generic to override native features on ppc machines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182049 91177308-0d34-0410-b5e6-96231b3b80d8
*	Create an new preheader in PPCCTRLoops to avoid counter register clobbers	Hal Finkel	2013-05-16	1	-0/+32
\| \| \| \| \| \| \| \| \| \| \| \| \|	Some IR-level instructions (such as FP <-> i64 conversions) are not chained w.r.t. the mtctr intrinsic and yet may become function calls that clobber the counter register. At the selection-DAG level, these might be reordered with the mtctr intrinsic causing miscompiles. To avoid this situation, if an existing preheader has instructions that might use the counter register, create a new preheader for the mtctr intrinsic. This extra block will be remerged with the old preheader at the MI level, but will prevent unwanted reordering at the selection-DAG level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182045 91177308-0d34-0410-b5e6-96231b3b80d8
*	PPC32 cannot form counter loops around i64 FP conversions	Hal Finkel	2013-05-16	1	-0/+28
	On PPC32, i64 FP conversions are implemented using runtime calls (which clobber the counter register). These must be excluded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182023 91177308-0d34-0410-b5e6-96231b3b80d8