aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen/PowerPC
Commit message (Collapse)AuthorAgeFilesLines
* During the CodeGenPrepare we often lower intrinsics (such as objsize)Nadav Rotem2012-08-141-3/+3
| | | | | | | | | | | | | and allow some optimizations to turn conditional branches into unconditional. This commit adds a simple control-flow optimization which merges two consecutive basic blocks which are connected by a single edge. This allows the codegen to operate on larger basic blocks. rdar://11973998 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161852 91177308-0d34-0410-b5e6-96231b3b80d8
* MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel2012-08-061-1/+1
| | | | | | | | | | | The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-041-0/+15
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor and check "onlyReadsMemory" before optimizing builtins.Bob Wilson2012-08-032-2/+2
| | | | | | | | | This patch is mostly just refactoring a bunch of copy-and-pasted code, but it also adds a check that the call instructions are readnone or readonly. That check was already present for sin, cos, sqrt, log2, and exp2 calls, but it was missing for the rest of the builtins being handled in this code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161282 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the remaining TCL-style quotes found in the testsuite. This isChandler Carruth2012-07-023-4/+4
| | | | | | | | | | | | | | | | | another mechanical change accomplished though the power of terrible Perl scripts. I have manually switched some "s to 's to make escaping simpler. While I started this to fix tests that aren't run in all configurations, the massive number of tests is due to a really frustrating fragility of our testing infrastructure: things like 'grep -v', 'not grep', and 'expected failures' can mask broken tests all too easily. Essentially, I'm deeply disturbed that I can change the testsuite so radically without causing any change in results for most platforms. =/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159547 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert the uses of '|&' to use '2>&1 |' instead, which works on oldChandler Carruth2012-07-023-3/+3
| | | | | | | | | | versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159544 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth2012-07-0227-68/+68
| | | | | | | | | | | | | | | | | | | | | | | | This was done through the aid of a terrible Perl creation. I will not paste any of the horrors here. Suffice to say, it require multiple staged rounds of replacements, state carried between, and a few nested-construct-parsing hacks that I'm not proud of. It happens, by luck, to be able to deal with all the TCL-quoting patterns in evidence in the LLVM test suite. If anyone is maintaining large out-of-tree test trees, feel free to poke me and I'll send you the steps I used to convert things, as well as answer any painful questions etc. IRC works best for this type of thing I find. Once converted, switch the LLVM lit config to use ShTests the same as Clang. In addition to being able to delete large amounts of Python code from 'lit', this will also simplify the entire test suite and some of lit's architecture. Finally, the test suite runs 33% faster on Linux now. ;] For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159525 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the PPC isel instruction.Hal Finkel2012-06-221-0/+23
| | | | | | | The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename fp-op fusion option (yet again) for compatibility with GCC option.Lang Hames2012-06-223-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159042 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames2012-06-223-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
* Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc ↵Hal Finkel2012-06-211-0/+22
| | | | | | | | stores on PPC. Thanks to Tobias von Koch for pointing out this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158932 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel2012-06-201-0/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DAG-combines for aggressive FMA formation.Lang Hames2012-06-193-3/+3
| | | | | | | | | | | | | | | | | | | | | | This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple.Jakob Stoklund Olesen2012-06-191-1/+1
| | | | | | The test was failing on Linux because of asm syntax differences. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158748 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen2012-06-191-0/+17
| | | | | | | | | | | | | The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-0/+47
| | | | | | PPC will now generate STWUX and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup trip-count finding for PPC CTR loops (and some bug fixes).Hal Finkel2012-06-162-0/+290
| | | | | | | | | | | | | | This cleans up the method used to find trip counts in order to form CTR loops on PPC. This refactoring allows the pass to find loops which have a constant trip count but also happen to end with a comparison to zero. This also adds explicit FIXMEs to mark two different classes of loops that are currently ignored. In addition, we now search through all potential induction operations instead of just the first. Also, we check the predicate code on the conditional branch and abort the transformation if the code is not EQ or NE, and we then make sure that the branch to be transformed matches the condition register defined by the comparison (multiple possible comparisons will be considered). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158607 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable ILP scheduling for all nodes by default on PPC.Hal Finkel2012-06-103-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Over the entire test-suite, this has an insignificantly negative average performance impact, but reduces some of the worst slowdowns from the anti-dep. change (r158294). Largest speedups: SingleSource/Benchmarks/Stanford/Quicksort - 28% SingleSource/Benchmarks/Stanford/Towers - 24% SingleSource/Benchmarks/Shootout-C++/matrix - 23% MultiSource/Benchmarks/SciMark2-C/scimark2 - 19% MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15% (matrix and automotive-bitcount were both in the top-5 slowdown list from the anti-dep. change) Largest slowdowns: MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28% MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26% MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21% SingleSource/Benchmarks/CoyoteBench/lpbench - 20% MultiSource/Applications/d/make_dparser - 16% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve ext/trunc patterns on PPC64.Hal Finkel2012-06-091-0/+1
| | | | | | | | | | The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that would leave self-moves in the final assembly. Replacing those patterns with ones based on the SUBREG builtins yields better-looking code. Thanks to Jakob and Owen for their suggestions in this matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable tail merging on PPC.Hal Finkel2012-06-091-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Tail merging had been disabled on PPC because it would disturb bundling decisions made during pre-RA scheduling on the 970 cores. Now, however, all bundling decisions are made during post-RA scheduling, and tail merging is generally beneficial (the average test-suite speedup is insignificantly positive). Largest test-suite speedups: MultiSource/Benchmarks/mediabench/gsm/toast/toast - 30% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 23% SingleSource/Benchmarks/Shootout-C++/ary - 21% SingleSource/Benchmarks/Stanford/Queens - 17% Largest slowdowns: MultiSource/Benchmarks/MiBench/security-sha/security-sha - 24% MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 22% MultiSource/Applications/JM/ldecod/ldecod - 14% MultiSource/Benchmarks/mediabench/g721/g721encode/encode - 9% This is improved by using full (instead of just critical) anti-dependency breaking, but doing so still causes miscompiles and so cannot yet be enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158259 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't run RAFast in the optimizing regalloc pipeline.Jakob Stoklund Olesen2012-06-084-4/+4
| | | | | | | | | | | The fast register allocator is not supposed to work in the optimizing pipeline. It doesn't make sense to compute live intervals, run full copy coalescing, and then run RAFast. Fast register allocation in the optimizing pipeline is better done by RABasic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158242 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable PPC CTR loop formation by default.Hal Finkel2012-06-082-2/+2
| | | | | | | | | | | | | | | | | | | | | | Thanks to Jakob's help, this now causes no new test suite failures! Over the entire test suite, this gives an average 1% speedup. The largest speedups are: SingleSource/Benchmarks/Misc/pi - 108% SingleSource/Benchmarks/CoyoteBench/lpbench - 54% MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50% SingleSource/Benchmarks/Shootout/ary3 - 32% SingleSource/Benchmarks/Shootout-C++/matrix - 30% The largest slowdowns are: MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30% MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25% MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22% MultiSource/Applications/d/make_dparser - -14% SingleSource/Benchmarks/Shootout-C++/ary - -13% In light of these slowdowns, additional profiling work is obviously needed! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the PPC CTR-Loops pass by default.Hal Finkel2012-06-082-2/+2
| | | | | | | | | | The pass itself works well, but the something in the Machine* infrastructure does not understand terminators which define registers. Without the ability to use the block-placement pass, etc. this causes performance regressions (and so is turned off by default). Turning off the analysis turns off the problems with the Machine* infrastructure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the new PPC CTR-Loops pass.Hal Finkel2012-06-081-0/+87
| | | | | | | | | The code which tests for an induction operation cannot assume that any ADDI instruction will have a register operand because the operand could also be a frame index; for example: %vreg16<def> = ADDI8 <fi#0>, 0; G8RC:%vreg16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158205 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form ↵Hal Finkel2012-06-081-0/+78
| | | | | | | | | | CTR-based loop branching code. This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are no longer otherwise used. Also, invalid preheader DebugLoc is not used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-041-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157935 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel2012-06-042-3/+3
| | | | | | | It seems that this no longer causes test suite failures on PPC64 (after r157159), and often gives a performance benefit, so it can be enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157911 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing PPC 64-bit stwu pattern.Hal Finkel2012-05-201-0/+28
| | | | | | | This seems to fix the remaining compile-time failures on PPC64 when compiling with -enable-ppc-preinc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157159 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove -join-physregs from the test suite.Jakob Stoklund Olesen2012-05-171-2/+4
| | | | | | | | | | | | | | This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157027 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead SD nodes after the combining pass. Fixes PR12201.Hal Finkel2012-04-161-0/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154786 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable prefetch generation on PPC64.Hal Finkel2012-04-011-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153851 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction itinerary for the PPC64 A2 core.Hal Finkel2012-04-011-0/+33
| | | | | | | This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
* Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky2012-03-251-8/+1
| | | | | | | | | | | | | | | | | | * Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix small-integer VAARG on SVR4 ABI PPC64.Hal Finkel2012-03-241-0/+20
| | | | | | | The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that are smaller than 64 bits be zero extended to 64 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153373 91177308-0d34-0410-b5e6-96231b3b80d8
* Test the section specification.Roman Divacky2012-02-271-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151552 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r151278 with fixes.Roman Divacky2012-02-271-2/+4
| | | | | | | | MCize function entry label emission on PowerPC64 properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151547 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r151278, breaks static linking.Hal Finkel2012-02-251-3/+2
| | | | | | | | | Reverting this because it breaks static linking on ppc64. Specifically, it may be linkonce_odr functions that are the problem. With this patch, if you link statically, calls to some functions end up calling their descriptor addresses instead of calling to their entry points. This causes the execution to fail with SIGILL (b/c the descriptor address just has some pointers, not code). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151433 91177308-0d34-0410-b5e6-96231b3b80d8
* X11/X2 loads around indirect calls on ppc64 should not be deleted.Hal Finkel2012-02-241-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151374 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash when a glue node contains an internal CopyToRegHal Finkel2012-02-241-0/+12
| | | | | | | This is necessary to support the existing ppc lowering code for indirect calls. Fixes PR12071. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151373 91177308-0d34-0410-b5e6-96231b3b80d8
* MCize function entry label emission on PowerPC64 properly.Roman Divacky2012-02-231-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151278 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the use of an alternate symbol for calculating a function's size.Hal Finkel2012-02-221-0/+18
| | | | | | | | | | | | | The standard function epilog includes a .size directive, but ppc64 uses an alternate local symbol to tag the actual start of each function. Until recently, binutils accepted the .size directive as: .size test1, .Ltmp0-test1 however, using this directive with recent binutils will result in the error: .size expression for XXX does not evaluate to a constant so we must use the label which actually tags the start of the function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151200 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a bad PowerPC test.Jakob Stoklund Olesen2012-02-211-160/+0
| | | | | | | | | | This test case was way too strict, matching the entire assembly output. Every non-trivial change to the ppc backend or -O0 pipeline required the test to be updated. It should be replaced with a test of the specific vaarg feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151105 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky2012-02-162-5/+13
| | | | | | | | | | | run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
* AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel2012-01-161-0/+40
| | | | | | does not have a corresponding SUnit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148260 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup stack/frame register define/kill states. This fixes two bugs:Hal Finkel2011-12-302-8/+14
| | | | | | | | 1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test). 2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case to make sure that the nop really does follow the bl on ppc64 elfHal Finkel2011-12-151-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146666 91177308-0d34-0410-b5e6-96231b3b80d8
* Manually upgrade the test suite to specify the flag to cttz and ctlz.Chandler Carruth2011-12-122-4/+4
| | | | | | | | | | | | | | | | | | | | | | | I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8
* Make CR spill and restore use a reserved register. These operations cannot ↵Hal Finkel2011-12-102-20/+20
| | | | | | use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146318 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514.Eli Friedman2011-12-091-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146219 91177308-0d34-0410-b5e6-96231b3b80d8
* delaying restore-cr changed assigned registers in some testsHal Finkel2011-12-062-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145963 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-13 19:54:57 +0000