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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-15/+16
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-7/+7
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-101-1/+1
| | | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add more special cases for opcodes to ensureSRegLimit()Tom Stellard2013-08-061-1/+1
| | | | | | Also factor out the register class lookup to its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-231-1/+1
| | | | | | | | | | | This increases the number of opportunites we have for folding. With the previous implementation we were unable to fold into any instructions other than the first when multiple instructions were selected from a single SDNode. Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186919 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-2/+2
| | | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186918 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: use capital letter for PV channelVincent Lejeune2013-06-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use depth first scheduling algorithmVincent Lejeune2013-05-171-1/+1
| | | | | | | It should increase PV substitution opportunities and lower gpr usage (pending computations path are "flushed" sooner) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182128 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add pattern for SHA-256 Ma functionTom Stellard2013-05-031-0/+18
| | | | | | This can be optimized using the BFI_INT instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add pattern for the BFI_INT instructionTom Stellard2013-04-191-0/+34
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
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