external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Update aosp/master LLVM for rebase to r230699.	Stephen Hines	2015-03-23	1	-11/+13
\| \| \| \|	Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
*	Update aosp/master LLVM for rebase to r222494.	Stephen Hines	2014-12-02	1	-53/+49
\| \| \| \|	Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
*	Update LLVM for 3.5 rebase (r209712).	Stephen Hines	2014-05-29	1	-1/+12
\| \| \| \|	Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
*	Update to LLVM 3.5a.	Stephen Hines	2014-04-24	1	-7/+7
\| \| \| \|	Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
*	R600/SI: Prefer SALU instructions for bit shift operations	Tom Stellard	2013-11-13	1	-7/+25
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600/SI: Change formatting of printed registers.	Matt Arsenault	2013-11-12	1	-4/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32	Tom Stellard	2013-10-23	1	-5/+10
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193212 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Non vector only instruction can be scheduled on trans unit	Vincent Lejeune	2013-09-04	1	-1/+1
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
*	Revert "R600: Non vector only instruction can be scheduled on trans unit"	Tom Stellard	2013-07-31	1	-1/+1
\| \| \| \| \| \|	This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Non vector only instruction can be scheduled on trans unit	Vincent Lejeune	2013-07-31	1	-1/+1
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
*	DAGCombiner: Pass the correct type to TargetLowering::isF(Abs\|Neg)Free	Tom Stellard	2013-07-23	1	-9/+21
\| \| \| \| \| \| \|	This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Expand vector FNEG	Tom Stellard	2013-07-23	1	-0/+26
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186913 91177308-0d34-0410-b5e6-96231b3b80d8