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* Update to LLVM 3.5a.Stephen Hines2014-04-241-4/+25
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-111-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-051-1/+1
| | | | | | It allows regalloc pass to remove them by trivially assigning associated reg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: use capital letter for PV channelVincent Lejeune2013-06-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-021-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer2013-03-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8
* Add R600 backendTom Stellard2012-12-111-0/+19
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-01-07 05:30:34 +0000