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Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
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Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
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Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
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r195514 | tstellar | 2013-11-22 15:07:58 -0800 (Fri, 22 Nov 2013) | 6 lines
R600/SI: Fixing handling of condition codes
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.
NOTE: This is a candidate for the 3.4 branch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195609 91177308-0d34-0410-b5e6-96231b3b80d8
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