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* Add GPRPair Register class to ARM.Jakob Stoklund Olesen2012-10-261-2/+2
| | | | | | | | | Some instructions in ARM require 2 even-odd paired GPRs. This patch adds support for such register class. Patch by Weiming Zhao! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166816 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129421 91177308-0d34-0410-b5e6-96231b3b80d8
* update tests for smarter BIC usageJim Grosbach2010-07-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108846 91177308-0d34-0410-b5e6-96231b3b80d8
* PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.Evan Cheng2010-06-291-25/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
* PR7458: Try commuting Thumb2 instruction operands to put them into 2-addressBob Wilson2010-06-241-1/+1
| | | | | | | form so they can be narrowed to 16-bit instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106762 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/packJim Grosbach2010-05-051-1/+1
| | | | | | | instructions to subtarget features and update tests to reflect. PR5717. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit versionJohnny Chen2010-03-041-10/+10
| | | | | | of either sxtb16 or uxtb16, and the unified syntax does not specify ".w". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert to FileCheckJim Grosbach2009-11-171-2/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89007 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
* Add thumb2 sign / zero extend with rotate instructions.Evan Cheng2009-07-031-0/+74
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
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