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* Allow a register to be redefined multiple times in a basic block.Jakob Stoklund Olesen2010-06-161-0/+21
| | | | | | | | | | | | | | | | | | | | LiveVariableAnalysis was a bit picky about a register only being redefined once, but that really isn't necessary. Here is an example of chained INSERT_SUBREGs that we can handle now: 68 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14 register: %reg1040 +[70,134:0) 76 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13 register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0) 0@78-(134) 1@70-(78) 84 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12 register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0) 0@86-(134) 1@70-(78) 2@78-(86) 92 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11 register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0) 0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94) rdar://problem/8096390 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106152 91177308-0d34-0410-b5e6-96231b3b80d8
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-162-1/+3
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the arm_aapcscc marker from the tests. It is the defaultRafael Espindola2010-06-153-9/+9
| | | | | | for the linux targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106029 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CoalescerPair helper class.Jakob Stoklund Olesen2010-06-151-0/+41
| | | | | | | | | | | | | | | | | | | | Given a copy instruction, CoalescerPair can determine which registers to coalesce in order to eliminate the copy. It deals with all the subreg fun to determine a tuple (DstReg, SrcReg, SubIdx) such that: - SrcReg is a virtual register that will disappear after coalescing. - DstReg is a virtual or physical register whose live range will be extended. - SubIdx is 0 when DstReg is a physical register. - SrcReg can be joined with DstReg:SubIdx. CoalescerPair::isCoalescable() determines if another copy instruction is compatible with the same tuple. This fixes some NEON miscompilations where shuffles are getting coalesced as if they were copies. The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105997 91177308-0d34-0410-b5e6-96231b3b80d8
* More tail call removal.Dale Johannesen2010-06-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105485 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tail call. A tail call version will follow.Dale Johannesen2010-06-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105438 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tail call to preserve this test. A tailDale Johannesen2010-06-031-1/+1
| | | | | | | | call version will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105422 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test not use tail calls. A tail callDale Johannesen2010-06-031-3/+3
| | | | | | | | version will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105419 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 RSBS instructions were being printed without the 'S' suffix.Bob Wilson2010-05-241-0/+9
| | | | | | | | Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR output and 'S' suffix in the same way as T2I_bin_s_irs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson2010-05-221-1/+2
| | | | | | | | | copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll tests, so I tweaked those tests to keep that code from being optimized away. Radar 7872877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
* t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to ↵Evan Cheng2010-05-191-6/+39
| | | | | | hoist more loads during machine LICM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the conditional for handling of sign_extend_inreg based onJim Grosbach2010-05-071-0/+22
| | | | | | | | | | whether the extract instructions are available. rdar://7956878 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103277 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/packJim Grosbach2010-05-058-9/+9
| | | | | | | instructions to subtarget features and update tests to reflect. PR5717. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
* fix copy/paste oops.Jim Grosbach2010-05-051-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add tests for ARMV7M divide instruction useJim Grosbach2010-05-051-0/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103120 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug which prevented tail merging of return instructions inDan Gohman2010-05-032-19/+16
| | | | | | | | | | | | | | | | | | | | | beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102907 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle register-to-register copies within the tGPR class.Bob Wilson2010-04-261-0/+73
| | | | | | | Radar 7896289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
* Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfieldJim Grosbach2010-04-221-0/+28
| | | | | | | | extraction. This fixes PR5998. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
* - Clean up some crappy code which deals with coalescing of copies which look atEvan Cheng2010-04-211-1/+1
| | | | | | | | extract_subreg / insert_subreg, etc. - Add support for more aggressive insert_subreg coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101971 91177308-0d34-0410-b5e6-96231b3b80d8
* Start function numbering at 0.Dan Gohman2010-04-174-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
* Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle ↵Evan Cheng2010-04-151-8/+8
| | | | | | is doing the right thing and codegen looks correct for both Thumb and Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP ↵Evan Cheng2010-04-151-0/+23
| | | | | | | | | directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 llvm is generating poor code for dynamic alloca, I'll fix that later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101383 91177308-0d34-0410-b5e6-96231b3b80d8
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-256-7/+7
| | | | | | Re-commit. This time complete with testsuite updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-177-11/+11
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-167-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-167-11/+11
| | | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.Bob Wilson2010-03-162-3/+3
| | | | | | | | This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98635 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for the change in r98586.Bob Wilson2010-03-161-0/+63
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98610 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable machine cse pass.Evan Cheng2010-03-101-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98132 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bitBob Wilson2010-03-081-0/+266
| | | | | | | | | immediate instructions cannot set the condition codes, so they do not have the extra cc_out operand. We hit an assertion during tail duplication because the instruction being duplicated had more operands that expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit versionJohnny Chen2010-03-041-10/+10
| | | | | | of either sxtb16 or uxtb16, and the unified syntax does not specify ".w". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a stack frame on ARM whenJakob Stoklund Olesen2010-02-241-0/+15
| | | | | | | | | | | - Function uses all scratch registers AND - Function does not use any callee saved registers AND - Stack size is too big to address with immediate offsets. In this case a register must be scavenged to calculate the address of a stack object, and the scavenger needs a spare register or emergency spill slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97071 91177308-0d34-0410-b5e6-96231b3b80d8
* LowerCall() should always do getCopyFromReg() to reference the stack pointer.Jim Grosbach2010-02-241-1/+1
| | | | | | | Machine instruction selection is much happier when operands are in virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97012 91177308-0d34-0410-b5e6-96231b3b80d8
* Last week we were generating code with duplicate induction variables in thisBob Wilson2010-02-151-0/+4
| | | | | | | | test, but the problem seems to have gone away today. Add a check to make sure it doesn't come back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96277 91177308-0d34-0410-b5e6-96231b3b80d8
* Besides removing phi cycles that reduce to a single value, also remove deadBob Wilson2010-02-132-2/+40
| | | | | | | | | phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96057 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply the new LoopStrengthReduction code, with compile time andDan Gohman2010-02-122-13/+17
| | | | | | | | | | | bug fixes, and with improved heuristics for analyzing foreign-loop addrecs. This change also flattens IVUsers, eliminating the stride-oriented groupings, which makes it easier to work with. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95975 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new pass on machine instructions to optimize away PHI cycles that Bob Wilson2010-02-121-0/+34
| | | | | | | | | | | | reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95951 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply coalescer fix for better cross-class coalescing.Jakob Stoklund Olesen2010-02-111-1/+1
| | | | | | This time with fixed test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95938 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.Bob Wilson2010-02-061-2/+2
| | | | | | | Radar 7614112. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95456 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert LoopStrengthReduce.cpp to pre-r94061 for now.Dan Gohman2010-01-222-17/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94123 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-implement the main strength-reduction portion of LoopStrengthReduction.Dan Gohman2010-01-212-13/+17
| | | | | | | | | | | | | | | This new version is much more aggressive about doing "full" reduction in cases where it reduces register pressure, and also more aggressive about rewriting induction variables to count down (or up) to zero when doing so reduces register pressure. It currently uses fairly simplistic algorithms for finding reuse opportunities, but it introduces a new framework allows it to combine multiple strategies at once to form hybrid solutions, instead of doing all full-reduction or all base+index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94061 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen2010-01-191-0/+53
| | | | | | | Since the mov is executed unconditionally, make sure that the add didn't have any predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
* Run the pre-register allocation tail duplication pass by default. RemoveBob Wilson2010-01-161-1/+1
| | | | | | | | the -pre-regalloc-taildup command-line option, and add a new -disable-early-taildup option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93597 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments.Jakob Stoklund Olesen2010-01-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92883 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Target hook to duplicate machine instructions.Jakob Stoklund Olesen2010-01-061-0/+87
| | | | | | | Some instructions refer to unique labels, and so cannot be trivially cloned with CloneMachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete useless trailing semicolons.Dan Gohman2010-01-051-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test pass on Linux.Nick Lewycky2009-12-161-9/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91521 91177308-0d34-0410-b5e6-96231b3b80d8
* Dynamic stack realignment use of sp register as source/dest registerAnton Korobeynikov2009-12-062-2/+2
| | | | | | | | | | in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode. Emit the following code instead: mov r4, sp bic r4, r4, #15 mov sp, r4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
* test case for IV-Users simplification loop improvementJim Grosbach2009-12-011-0/+128
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90260 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable predication of NEON instructions in Thumb2 mode.Evan Cheng2009-11-241-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89748 91177308-0d34-0410-b5e6-96231b3b80d8
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