| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Select an OR with immediate as an ADD if the input bits are known zero. This ↵ | Evan Cheng | 2010-01-11 | 1 | -1/+7 |
| | | | | | | | allow the instruction to be 3address-fied if needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93152 91177308-0d34-0410-b5e6-96231b3b80d8 | ||||
| * | Eliminate more uses of llvm-as and llvm-dis. | Dan Gohman | 2009-09-08 | 1 | -1/+1 |
| | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8 | ||||
| * | Fix PR4254. | Torok Edwin | 2009-05-23 | 1 | -0/+14 |
| The DAGCombiner created a negative shiftamount, stored in an unsigned variable. Later the optimizer eliminated the shift entirely as being undefined. Example: (srl (shl X, 56) 48). ShiftAmt is 4294967288. Fix it by checking that the shiftamount is positive, and storing in a signed variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72331 91177308-0d34-0410-b5e6-96231b3b80d8 | |||||
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