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* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-10/+10
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LiveInterval::isZeroLength about null SlotIndexes.Jakob Stoklund Olesen2011-05-161-11/+0
| | | | | | | | | | | | When instructions are deleted, they leave tombstone SlotIndex entries. The isZeroLength method should ignore these null indexes. This causes RABasic to sometimes spill a callee-saved register in the abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing register allocation according to spill weight can cause more registers to be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131436 91177308-0d34-0410-b5e6-96231b3b80d8
* Prepare remaining tests for -join-physreg going away.Jakob Stoklund Olesen2011-05-041-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130893 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix one more batch of X86 tests to be register allocation dependent.Jakob Stoklund Olesen2011-04-051-2782/+2793
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128919 91177308-0d34-0410-b5e6-96231b3b80d8
* Experiment with changing the default 32-bit linux stack alignment toEric Christopher2011-01-131-56/+70
| | | | | | | 16 bytes for PR8969. Update all testcases accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123367 91177308-0d34-0410-b5e6-96231b3b80d8
* Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack inEvan Cheng2011-01-031-159/+159
| | | | | | | | | | | | prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if the adjustment is 4 in 32-bit mode. In the epilogue, takes care to pop to a caller-saved register that's not live at the exit (either return or tailcall instruction). rdar://8771137 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122783 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an inconsistency in the x86 backend that led it to reject "calll foo" onChris Lattner2010-09-221-305/+305
| | | | | | | | | | | | | x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly named "callq", so this only impacted x86-32. This fixes rdar://8456370 - llvm-mc rejects 'calll' This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call, I will file a bugzilla. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
* Start function numbering at 0.Dan Gohman2010-04-171-488/+488
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove "tail" keywords. These calls are not intended to be tail calls.Dan Gohman2009-12-181-33/+33
| | | | | | | | This protects this test from depending on codegen not performing the tail call optimization by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91648 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction fixes, added instructions, and AsmString changes in theSean Callanan2009-12-181-165/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | X86 instruction tables. Also (while I was at it) cleaned up the X86 tables, removing tabs and 80-line violations. This patch was reviewed by Chris Lattner, but please let me know if there are any problems. * X86*.td Removed tabs and fixed 80-line violations * X86Instr64bit.td (IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW) Added (CALL, CMOV) Added qualifiers (JMP) Added PC-relative jump instruction (POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate that it is 64-bit only (ambiguous since it has no REX prefix) (MOV) Added rr form going the other way, which is encoded differently (MOV) Changed immediates to offsets, which is more correct; also fixed MOV64o64a to have to a 64-bit offset (MOV) Fixed qualifiers (MOV) Added debug-register and condition-register moves (MOVZX) Added more forms (ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which (as with MOV) are encoded differently (ROL) Made REX.W required (BT) Uncommented mr form for disassembly only (CVT__2__) Added several missing non-intrinsic forms (LXADD, XCHG) Reordered operands to make more sense for MRMSrcMem (XCHG) Added register-to-register forms (XADD, CMPXCHG, XCHG) Added non-locked forms * X86InstrSSE.td (CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ) Added * X86InstrFPStack.td (COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP, FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X, FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM, FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE, FXRSTOR) Added (FCOM, FCOMP) Added qualifiers (FSTENV, FSAVE, FSTSW) Fixed opcode names (FNSTSW) Added implicit register operand * X86InstrInfo.td (opaque512mem) Added for FXSAVE/FXRSTOR (offset8, offset16, offset32, offset64) Added for MOV (NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR, LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS, LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT, LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC, CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC, SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL, VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXOFF, VMXON) Added (NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier (JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, JCXZ) Added 32-bit forms (MOV) Changed some immediate forms to offset forms (MOV) Added reversed reg-reg forms, which are encoded differently (MOV) Added debug-register and condition-register moves (CMOV) Added qualifiers (AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV (BT) Uncommented memory-register forms for disassembler (MOVSX, MOVZX) Added forms (XCHG, LXADD) Made operand order make sense for MRMSrcMem (XCHG) Added register-register forms (XADD, CMPXCHG) Added unlocked forms * X86InstrMMX.td (MMX_MOVD, MMV_MOVQ) Added forms * X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table change * X86RegisterInfo.td: Added debug and condition register sets * x86-64-pic-3.ll: Fixed testcase to reflect call qualifier * peep-test-3.ll: Fixed testcase to reflect test qualifier * cmov.ll: Fixed testcase to reflect cmov qualifier * loop-blocks.ll: Fixed testcase to reflect call qualifier * x86-64-pic-11.ll: Fixed testcase to reflect call qualifier * 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call qualifier * x86-64-pic-2.ll: Fixed testcase to reflect call qualifier * live-out-reg-info.ll: Fixed testcase to reflect test qualifier * tail-opts.ll: Fixed testcase to reflect call qualifiers * x86-64-pic-10.ll: Fixed testcase to reflect call qualifier * bss-pagealigned.ll: Fixed testcase to reflect call qualifier * x86-64-pic-1.ll: Fixed testcase to reflect call qualifier * widen_load-1.ll: Fixed testcase to reflect call qualifier git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on post-alloc scheduling for x86.Evan Cheng2009-10-181-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
* turn on -experimental-asm-printer for x86 / AT&T by default.Chris Lattner2009-09-111-488/+488
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81532 91177308-0d34-0410-b5e6-96231b3b80d8
* disable the new asmprinter by default. Both the Mangler and MCSymbolChris Lattner2009-09-091-488/+488
| | | | | | | printing stuff are quoting symbols now, breaking objc testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81319 91177308-0d34-0410-b5e6-96231b3b80d8
* turn the mcinst asmprinter on by default for x86, tweaking two tests toChris Lattner2009-09-091-488/+488
| | | | | | | expect the slight syntax differences in the generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81305 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-081-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch abi-isel.ll to FileCheck; it's not much faster, but it now tests a lot Daniel Dunbar2009-08-251-166/+7973
| | | | | | | | | | more and is much nicer to the OS. - Dan, please check. If there are parts of the test you think I should strip out so it doesn't cause random failures let me know (there are still some PIC label numbers in it, for example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80019 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an x86 code size regression: prefer RIP-relative addressingDan Gohman2009-08-201-69/+69
| | | | | | | | | over absolute addressing even in non-PIC mode (unless the address has an index or something else incompatible), because it has a smaller encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79553 91177308-0d34-0410-b5e6-96231b3b80d8
* fix x86-64 static codegen to materialize the address of a global with movl ↵Chris Lattner2009-07-111-37/+37
| | | | | | | | | | | | | | | | | | | | instead of lea. It is better for code size (and presumably efficiency) to use: movl $foo, %eax rather than: leal foo, eax Both give a nice zero extending "move immediate" instruction, the former is just smaller. Note that global addresses should be handled different by the x86 backend, but I chose to follow the style already in place and add more fixme's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75403 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR4533, which is about buggy codegen in x86-64 -static mode.Chris Lattner2009-07-111-20/+557
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically, using: lea symbol(%rip), %rax is not valid in -static mode, because the current RIP may not be within 32-bits of "symbol" when an app is built partially pic and partially static. The fix for this is to compile it to: lea symbol, %rax It would be better to codegen this as: movq $symbol, %rax but that will come next. The hard part of fixing this bug was fixing abi-isel, which was actively testing for the wrong behavior. Also, the RUN lines are completely impossible to understand what they are testing. To help with this, convert the -static x86-64 codegen tests to use filecheck. This is much more stable and makes it more clear what the codegen is expected to be. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75382 91177308-0d34-0410-b5e6-96231b3b80d8
* For Darwin / x86_64, override -relocation-model=static to pic if the output ↵Evan Cheng2009-06-031-20/+0
| | | | | | | | | is assembly since Darwin assembler does not really support -static codeine. I view this as a temporary workaround until the assembler / linker changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72806 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r72734. The Darwin assembler doesn't support the staticDan Gohman2009-06-031-2/+2
| | | | | | | | relocation model on x86-64. Higher level logic should override the relocation model to PIC on x86_64-apple-darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72746 91177308-0d34-0410-b5e6-96231b3b80d8
* On Darwin x86_64 small code model doesn't guarantee code address fits in 32-bit.Evan Cheng2009-06-021-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72734 91177308-0d34-0410-b5e6-96231b3b80d8
* In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matchingRafael Espindola2009-04-121-4/+4
| | | | | | | | only if symbolic addresses are RIP relatives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68924 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase that covers a wide variety of ABI isel cases.Dan Gohman2009-03-141-0/+1322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67003 91177308-0d34-0410-b5e6-96231b3b80d8
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