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* Enable MI Sched for x86.Andrew Trick2013-10-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Temporarily enable MI-Sched on X86."Andrew Trick2013-06-251-2/+2
| | | | | | This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily enable MI-Sched on X86.Andrew Trick2013-06-241-2/+2
| | | | | | | Sorry for the unit test churn. I'll try to make the change permanently next time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on post-alloc scheduling for x86.Evan Cheng2009-10-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix this test to account for a movl $0 being emitted as an xor now,Dan Gohman2009-10-141-2/+3
| | | | | | | and convert it to FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84065 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-081-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test.Evan Cheng2008-09-051-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55849 91177308-0d34-0410-b5e6-96231b3b80d8
* If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM ↵Evan Cheng2008-09-051-1/+1
| | | | | | registers for fastcc calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
* For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing ↵Evan Cheng2008-09-041-0/+19
scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55807 91177308-0d34-0410-b5e6-96231b3b80d8
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