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	Commit message (Collapse)	Author	Age	Files	Lines
*	Teach the x86 backend a couple tricks for dealing with v16i8 sra by a ↵	Eli Friedman	2011-11-01	1	-0/+20
\| \| \| \| \| \|	constant splat value. Fixes PR11289. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143498 91177308-0d34-0410-b5e6-96231b3b80d8
*	X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift ↵	Benjamin Kramer	2011-10-30	1	-0/+18
\| \| \| \| \| \|	and zero out the bits where zeros should've been shifted in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143315 91177308-0d34-0410-b5e6-96231b3b80d8
*	Fix pr11266.	Nadav Rotem	2011-10-30	1	-2/+14
\| \| \| \| \| \| \| \| \| \| \|	On x86: (shl V, 1) -> add V,V Hardware support for vector-shift is sparse and in many cases we scalarize the result. Additionally, on sandybridge padd is faster than shl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143311 91177308-0d34-0410-b5e6-96231b3b80d8
*	Enable element promotion type legalization by deafault.	Nadav Rotem	2011-10-16	1	-2/+2
\| \| \| \| \| \| \| \|	Changed tests which assumed that vectors are legalized by widening them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142152 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a ↵	Nadav Rotem	2011-05-11	1	-0/+142
	splat vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131179 91177308-0d34-0410-b5e6-96231b3b80d8