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* Handle REG_SEQUENCE with implicitly defined operands.Jakob Stoklund Olesen2011-07-281-0/+21
| | | | | | | | | | | | | Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136401 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns to generate copies for extract_subvector instead ofBruno Cardoso Lopes2011-07-281-3/+3
| | | | | | | using vextractf128. This will reduce the number of issued instruction for several avx codes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136323 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few patterns to match allzeros without having to use the fp unit.Bruno Cardoso Lopes2011-07-281-1/+1
| | | | | | | Take advantage that the 128-bit vpxor zeros the higher part and use it. This also fixes PR10491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136321 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also moveBruno Cardoso Lopes2011-07-281-0/+14
| | | | | | a convert pattern close to the instruction definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
* The vpermilps and vpermilpd have different behaviour regarding theBruno Cardoso Lopes2011-07-271-0/+16
| | | | | | | | | usage of the shuffle bitmask. Both work in 128-bit lanes without crossing, but in the former the mask of the high part is the same used by the low part while in the later both lanes have independent masks. Handle this properly and and add support for vpermilpd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
* It is quiet possible that inlined function body is split into multiple ↵Devang Patel2011-07-271-0/+140
| | | | | | chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136196 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate copies of undefined values during coalescing.Jakob Stoklund Olesen2011-07-261-0/+27
| | | | | | | | | | These copies would coalesce easily, but the resulting value would be defined by a deleted instruction. Now we also remove the undefined value number from the destination register. This fixes PR10503. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136174 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test.Benjamin Kramer2011-07-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136170 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a neat little two's complement hack for x86.Benjamin Kramer2011-07-261-0/+11
| | | | | | | | | | On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add, which can be commuted and encoded efficiently. This code is generated for __builtin_clz and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136167 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize unpckh* masks and match 256-bit versions. The new versions areBruno Cardoso Lopes2011-07-266-85/+58
| | | | | | | different from the previous 128-bit because they work in lanes. Update a few comments and add testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent x86-specific DAGCombine from creating nodes with illegal type (which ↵Eli Friedman2011-07-261-2/+1
| | | | | | could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136148 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck'ize test.Jim Grosbach2011-07-261-20/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136135 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL this test while I investigate it; it's failing for an unexpected reason.Eli Friedman2011-07-261-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136131 91177308-0d34-0410-b5e6-96231b3b80d8
* Add obvious missing case to switch. PR10497.Eli Friedman2011-07-261-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136130 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 256-bit isel for movsldup/movshdupBruno Cardoso Lopes2011-07-261-0/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136051 91177308-0d34-0410-b5e6-96231b3b80d8
* Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128Bruno Cardoso Lopes2011-07-251-0/+12
| | | | | | This also fixes PR10452 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
* - Handle special scalar_to_vector case: splats. Using a native 128-bitBruno Cardoso Lopes2011-07-252-4/+23
| | | | | | | | | | shuffle before inserting on a 256-bit vector. - Add AVX versions of movd/movq instructions - Introduce a few COPY patterns to match insert_subvector instructions. This turns a trivial insert_subvector instruction into a register copy, coalescing the xmm into a ymm and avoid emiting on more instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136002 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to fix test failure reported on llvm-commits.Eli Friedman2011-07-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135995 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure this DAGCombine actually returns an UNDEF of the correct type; ↵Eli Friedman2011-07-251-2/+18
| | | | | | PR10476. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135993 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of an incorrect optimization for shuffles with PALIGNR and simplify ↵Eli Friedman2011-07-251-7/+22
| | | | | | | | | | isPALIGNRMask. Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135980 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly handle <undef> tied uses when rewriting after a split.Jakob Stoklund Olesen2011-07-241-0/+25
| | | | | | | | | | | This fixes PR10463. A two-address instruction with an <undef> use operand was incorrectly rewritten so the def and use no longer used the same register, violating the tie constraint. Fix this by always rewriting <undef> operands with the register a def operand would use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135885 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test check!Bruno Cardoso Lopes2011-07-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135802 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10422 by adding the necessary AVX UCOMISD memory versions toBruno Cardoso Lopes2011-07-221-0/+28
| | | | | | load folding logic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135801 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64Rafael Espindola2011-07-221-0/+26
| | | | | | too. Patch by Jeff Muizelaar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135789 91177308-0d34-0410-b5e6-96231b3b80d8
* -Inspected a AVX code block added by someone in early Feb. This was never usedBruno Cardoso Lopes2011-07-222-2/+2
| | | | | | | | | | | | | | | | and was actually very wrong, fix it and make it simpler. Also remove the ConcatVectors function, which is unused now. - Fix a introduction of useless nodes in r126664 and r126264. The VUNPCKL* should never be introduced cause we don't want duplicate nodes for 128 AVX and non-AVX modes, the actual instruction difference only exists during isel, but not for target specific DAG nodes. We only introduce V* target nodes when there is no 128-bit version already there. - Fix a fragile test and make it more useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
* Although we already support this, add testcases for consistencyBruno Cardoso Lopes2011-07-221-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135728 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DAGCombine for transforming 128->256 casts into a simpleBruno Cardoso Lopes2011-07-221-0/+26
| | | | | | vxorps + vinsertf128 pair of instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
* - Register v16i16 as valid VR256 register classBruno Cardoso Lopes2011-07-211-1/+12
| | | | | | | | - Add more bitcasts for v16i16 - Since 135661 and 135662 already added the splat logic, just add one more splat test for v16i16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
* While emitting constant value, look through derived type and use underlying ↵Devang Patel2011-07-201-0/+61
| | | | | | basic type to determine size and signness of the constant value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135627 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.Eli Friedman2011-07-201-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135595 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng2011-07-201-1/+1
| | | | | | | | | TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
* New pointer rotate test.Eric Christopher2011-07-201-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-191-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.Evan Cheng2011-07-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka2011-07-191-16/+16
| | | | | | | ANDi, when the instruction does not have any immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundant instructions.Akira Hatanaka2011-07-191-10/+5
| | | | | | | | | | - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the zext / sext instructions.Richard Osborne2011-07-191-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the testct, testwct instructions.Richard Osborne2011-07-191-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135475 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for the peek and endin instructions.Richard Osborne2011-07-191-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135474 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-191-1/+0
| | | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r135423.Devang Patel2011-07-191-120/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135454 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck-ize a couple tests.Eli Friedman2011-07-182-4/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135427 91177308-0d34-0410-b5e6-96231b3b80d8
* During bottom up fast-isel, instructions emitted to materalize registers are ↵Devang Patel2011-07-181-0/+120
| | | | | | | | | at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. [take 2] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135423 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not treat atomic.load.sub differently than other atomic binary intrinsics.Akira Hatanaka2011-07-181-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135418 91177308-0d34-0410-b5e6-96231b3b80d8
* Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from Akira Hatanaka2011-07-181-24/+18
| | | | | | | | | moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135415 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a crash when building 177.mesa for armv6.Jakob Stoklund Olesen2011-07-181-0/+32
| | | | | | | | | | | | When splitting a live range immediately before an LDR_POST instruction that redefines the address register, make sure to use the correct value number in leaveIntvBefore. We need the value number entering the instruction. <rdar://problem/9793765> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135413 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 128-bit sqrt versionsBruno Cardoso Lopes2011-07-181-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete empty unused file.Nick Lewycky2011-07-181-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135379 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 128-bit patterns for sint_to_fpBruno Cardoso Lopes2011-07-161-1/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
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