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* ARM: don't expand atomicrmw inline on Cortex-M0Tim Northover2013-10-251-0/+1
* LegalizeDAG: allow libcalls for max/min atomic operationsTim Northover2013-10-251-0/+24
* ARM: Test r193381 a bit more thoroughly.Jim Grosbach2013-10-241-0/+2
* ARM: Tweak usage of '*vfp' compiler_rt functions.Jim Grosbach2013-10-241-2/+2
* ARM: Use non-VFP softcalls on embedded Darwinish targetsTim Northover2013-10-241-0/+22
* Added test for -elf configuration, to see that _alloca call is properly Yaron Keren2013-10-241-9/+16
* Make sure SP is always aligned on a 2 byte boundaryJob Noorman2013-10-241-0/+17
* [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.Amara Emerson2013-10-241-0/+17
* AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsicsElena Demikhovsky2013-10-241-0/+15
* Replace sse41/sse42 with sse4.1/sse4.2 in test command lines to fix bots.Craig Topper2013-10-242-2/+2
* Add non-AVX tests for AES intrinsics.Craig Topper2013-10-241-0/+48
* Add tests for SSE intrinsics in non-avx mode by copying from the AVX test cas...Craig Topper2013-10-246-0/+1704
* X86: Custom lower sext v16i8 to v16i16, and the corresponding truncate.Benjamin Kramer2013-10-234-3/+37
* X86: Custom lower zext v16i8 to v16i16.Benjamin Kramer2013-10-232-0/+21
* Fix PR17631Michael Liao2013-10-231-0/+22
* [mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrins...Daniel Sanders2013-10-231-0/+69
* R600/SI: fix MIMG writemask adjustementTom Stellard2013-10-231-0/+93
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-235-115/+502
* R600/SI: Add support for i64 bitwise orTom Stellard2013-10-231-4/+17
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-231-5/+10
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-0/+39
* AVX-512: aligned / unaligned load and store for 512-bit integer vectors.Elena Demikhovsky2013-10-221-0/+28
* Add testcase for PR3168. It was fixed over time.Bill Wendling2013-10-221-0/+21
* Fix spelling, grammar, and match naming convention for test files.Eric Christopher2013-10-211-1/+1
* [AArch64] Add the constraint to NEON scalar mla/mls instructions.Chad Rosier2013-10-211-20/+24
* Fix CodeGen for vectors of pointers with address spaces.Matt Arsenault2013-10-211-0/+30
* Fix CodeGen for different size address space GEPsMatt Arsenault2013-10-211-0/+10
* X86 vector element shift-by-immediate instructions take i8 immediates. MakeLang Hames2013-10-212-4/+4
* AVX-512: MUL operation lowering for v8i64Elena Demikhovsky2013-10-211-1/+10
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-211-27/+27
* Emit prefix data after debug and EH directives.Peter Collingbourne2013-10-201-0/+2
* Update PPC loop tests after SCEV non-unit-stride checkin r193015.Andrew Trick2013-10-192-24/+12
* Test case for r192957David Majnemer2013-10-181-0/+21
* [PATCH] Fix PR17168 (DAG scheduler inserts DBG_VALUE before PHI with fast-isel)Bill Schmidt2013-10-181-0/+520
* [AArch64] Add support for NEON scalar extract narrow instructions.Chad Rosier2013-10-181-0/+104
* [mips][msa] Added a regression test that depended on multiple patches to pass.Daniel Sanders2013-10-181-0/+150
* Revert "Re-commit r192758 - MC: quote tricky symbol names in asm output"Hans Wennborg2013-10-183-7/+5
* 17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targetsDavid Peixotto2013-10-172-0/+1580
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-171-0/+75
* Add testcase to make sure we don't generate a compact unwind section for ELF ...Bill Wendling2013-10-171-0/+48
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-171-0/+26
* Fix tests not to depend on specific regalloc or instruction order.Benjamin Kramer2013-10-172-4/+4
* Fix r192888: test/CodeGen/Mips/msa/3r_ld_st.ll should have been deletedDaniel Sanders2013-10-171-149/+0
* Replace sra with srl if a single sign bit is requiredRichard Sandiford2013-10-172-5/+16
* Fix edge condition in DAGCombiner to improve codegen of shift sequences.Andrea Di Biagio2013-10-171-0/+8
* x86: Move bitcasts outside concat_vector.Jim Grosbach2013-10-171-1/+24
* Re-commit r192758 - MC: quote tricky symbol names in asm outputHans Wennborg2013-10-173-5/+7
* [AArch64] Add support for NEON scalar negate instruction.Chad Rosier2013-10-161-0/+12
* [AArch64] Add support for NEON scalar absolute value instruction.Chad Rosier2013-10-161-0/+12
* Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,Yunzhong Gao2013-10-161-0/+3
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