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* Change allowsUnalignedMemoryAccesses to take type argument since some targetsEvan Cheng2009-08-151-12/+27
| | | | | | | | | | | support unaligned mem access only for certain types. (Should it be size instead?) ARM v7 supports unaligned access for i16 and i32, some v6 variants support it as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79127 91177308-0d34-0410-b5e6-96231b3b80d8
* implement support for CHECK-NEXT: in filecheck.Chris Lattner2009-08-151-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79123 91177308-0d34-0410-b5e6-96231b3b80d8
* Refine EarlyClobber assert in register scavenger.Jakob Stoklund Olesen2009-08-151-0/+42
| | | | | | | | | | | | | | It is legal for an inline asm operand to use an earlyclobber register if the use operand is tied to the earlyclobber operand. The issue is discussed here: http://gcc.gnu.org/ml/gcc/1999-04n/msg00431.html We should perhaps let only the machine code verifier worry about these finer details. EarlyClobber operands are not really interesting to the scavenger. This fixes PR4528 for the third time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79122 91177308-0d34-0410-b5e6-96231b3b80d8
* specify a target triple so global variable manglings are consistent etc.Chris Lattner2009-08-151-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79118 91177308-0d34-0410-b5e6-96231b3b80d8
* convert to filecheck.Chris Lattner2009-08-151-3/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79117 91177308-0d34-0410-b5e6-96231b3b80d8
* rename this test to sse2.llChris Lattner2009-08-151-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79116 91177308-0d34-0410-b5e6-96231b3b80d8
* merge a bunch more sse3 tests into sse3.llChris Lattner2009-08-1511-174/+252
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79115 91177308-0d34-0410-b5e6-96231b3b80d8
* convert test to filecheck format.Chris Lattner2009-08-151-7/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79114 91177308-0d34-0410-b5e6-96231b3b80d8
* rename testChris Lattner2009-08-151-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79113 91177308-0d34-0410-b5e6-96231b3b80d8
* this is a test for sse3, simplify it.Chris Lattner2009-08-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79112 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't setCalleeSavedInfoValid() until spills are interted.Jakob Stoklund Olesen2009-08-151-0/+10
| | | | | | | | | | In a naked function, the flag is never set and getPristineRegs() returns an empty list. That means naked functions are able to clobber callee saved registers, but that is the whole point of naked functions. This fixes PR4716. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79096 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XFAIL testcase for setcc undef.Jakob Stoklund Olesen2009-08-151-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79093 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XFAIL test case for a scavenger assert.Jakob Stoklund Olesen2009-08-151-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79092 91177308-0d34-0410-b5e6-96231b3b80d8
* Update LocalRewriter::DistanceMap when inserting stack loads.Jakob Stoklund Olesen2009-08-151-0/+25
| | | | | | | | In the included test case, a stack load was not included in DistanceMap. That caused TransferDeadness to ignore the instruction, leading to a scavenger assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79090 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix tests.Evan Cheng2009-08-152-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79086 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on if-conversion for thumb2.Evan Cheng2009-08-153-0/+189
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
* use XCore-specific section with xcore specific cp/dp flags to restore Chris Lattner2009-08-152-2/+0
| | | | | | | | | support for globals going into the appropriate sections with the flags. This hopefully finishes unbreaking the previous behavior that I broke before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79079 91177308-0d34-0410-b5e6-96231b3b80d8
* On x86-64, for a varargs function, don't store the xmm registers toDan Gohman2009-08-151-0/+20
| | | | | | | | the register save area if %al is 0. This avoids touching xmm regsiters when they aren't actually used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79061 91177308-0d34-0410-b5e6-96231b3b80d8
* Leaf functions which do not save CSRs can be frameless even with ↵Evan Cheng2009-08-141-0/+6
| | | | | | -disable-fp-elim. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79039 91177308-0d34-0410-b5e6-96231b3b80d8
* Also shrink immediate branches; also more assembler workarounds.Evan Cheng2009-08-142-6/+77
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79014 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly handle indirect win64 args when they're passed in memoryAnton Korobeynikov2009-08-141-0/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79009 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink ADR and LDR from constantpool late during constantpool island pass.Evan Cheng2009-08-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove HasCrazyBSS and add a flag in TAI to indicate that '.section' Bruno Cardoso Lopes2009-08-131-0/+8
| | | | | | | must be emitted for PowerPC-Linux '.bss' section git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78958 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 78892 and 78895, these break generating working executables onDaniel Dunbar2009-08-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | x86_64-apple-darwin10. --- Reverse-merging r78895 into '.': U test/CodeGen/PowerPC/2008-12-12-EH.ll U lib/Target/DarwinTargetAsmInfo.cpp --- Reverse-merging r78892 into '.': U include/llvm/Target/DarwinTargetAsmInfo.h U lib/Target/X86/X86TargetAsmInfo.cpp U lib/Target/X86/X86TargetAsmInfo.h U lib/Target/ARM/ARMTargetAsmInfo.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/ARMTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.h U lib/Target/PowerPC/PPCTargetMachine.cpp G lib/Target/DarwinTargetAsmInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8
* reintroduce support for Mips "small" section handling. This is Chris Lattner2009-08-131-0/+32
| | | | | | | | | implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78900 91177308-0d34-0410-b5e6-96231b3b80d8
* tPOP_RET now has predicate operands.Evan Cheng2009-08-131-0/+737
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78898 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typo, add 10.6 version of test for my previous patch.Chris Lattner2009-08-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78895 91177308-0d34-0410-b5e6-96231b3b80d8
* It's ok to spill a tGPR register as long as it's still allocated a low register.Evan Cheng2009-08-131-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78893 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MCSectionELF to represent a section semantically instead ofBruno Cardoso Lopes2009-08-131-0/+18
| | | | | | | | syntactically as a string, very similiar to what Chris did with MachO. The parsing support and validation is not introduced yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78890 91177308-0d34-0410-b5e6-96231b3b80d8
* Various AsmWriter output cleanups. Use WriteAsOperand instead ofDan Gohman2009-08-132-4/+4
| | | | | | | PrintUnmangledNameSafely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78878 91177308-0d34-0410-b5e6-96231b3b80d8
* Use WriteAsOperand to print BasicBlock names.Dan Gohman2009-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78838 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate Neon VTBL and VTBX instructions from the corresponding intrinsics.Bob Wilson2009-08-121-0/+109
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78835 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for 78821, sort of. While that bug is nondeterministic,Dale Johannesen2009-08-121-0/+176
| | | | | | | | this test failed consistently on a Darwin build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78822 91177308-0d34-0410-b5e6-96231b3b80d8
* one last (?) bad x86 triple test.Chris Lattner2009-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78801 91177308-0d34-0410-b5e6-96231b3b80d8
* fix some pastos in triple lines.Chris Lattner2009-08-121-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78800 91177308-0d34-0410-b5e6-96231b3b80d8
* another bogus tripleChris Lattner2009-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78798 91177308-0d34-0410-b5e6-96231b3b80d8
* fix another broken target triple.Chris Lattner2009-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78796 91177308-0d34-0410-b5e6-96231b3b80d8
* fix an incorrect target triple.Chris Lattner2009-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78795 91177308-0d34-0410-b5e6-96231b3b80d8
* add nounwindChris Lattner2009-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78791 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an Darwin assembler workaround.Evan Cheng2009-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78777 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink ADDS, ADC, RSB, and SUBS.Evan Cheng2009-08-129-20/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78776 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrinkify Thumb2 r = add sp, imm.Evan Cheng2009-08-111-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78745 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
* now that these are in file-check format, we can merge them togetherChris Lattner2009-08-115-56/+49
| | | | | | | into one bigger test (which runs faster) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78672 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the previous accidental commit. Now shrinking common Thumb2 load / store ↵Evan Cheng2009-08-117-34/+73
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78659 91177308-0d34-0410-b5e6-96231b3b80d8
* Rebuild RegScavenger::DistanceMap each time it is needed.Jakob Stoklund Olesen2009-08-111-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register scavenger maintains a DistanceMap that maps MI pointers to their distance from the top of the current MBB. The DistanceMap is built incrementally in forward() and in bulk in findFirstUse(). It is used by scavengeRegister() to determine which candidate register has the longest unused interval. Unfortunately the DistanceMap contents can become outdated. The first time scavengeRegister() is called, the DistanceMap is filled to cover the MBB. If then instructions are inserted in the MBB (as they always are following scavengeRegister()), the recorded distances are too short. This causes bad behaviour in the included test case where a register use /after/ the current position is ignored because findFirstUse() thinks is is /before/ the current position. A "using an undefined register" assertion follows promptly. The fix is to build a fresh DistanceMap at the top of scavengeRegister(), and discard it after use. This means that DistanceMap is no longer needed as a RegScavenger member variable, and forward() doesn't need to update it. The fix then discloses issue number two in the same test case: The candidate search in scavengeRegister() finds a CSR that has been saved in the prologue, but is currently unused. It would be both inefficient and wrong to spill such a register in the emergency spill slot. In the present case, the emergency slot restore is placed immediately before the normal epilogue restore, leading to a "Redefining a live register" assertion. Fix number two: When scavengerRegister() stumbles upon an unused register that is overwritten later in the MBB, return that register early. It is important to verify that the register is defined later in the MBB, otherwise it might be an unspilled CSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78650 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more Neon tests to use FileCheck.Bob Wilson2009-08-112-16/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78648 91177308-0d34-0410-b5e6-96231b3b80d8
* Use vAny type to get rid of Neon intrinsics that differed only in whetherBob Wilson2009-08-1119-164/+164
| | | | | | | | | | | | the overloaded vector types allowed floating-point or integer vector elements. Most of these operations actually depend on the element type, so bitcasting was not an option. If you include the vpadd intrinsics that I updated earlier, this gets rid of 20 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
* Use new EVT::vAny type to combine Neon intrinsics for VPADD.Bob Wilson2009-08-111-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78632 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch ↵Evan Cheng2009-08-1026-80/+240
| | | | | | of thumb2 tests to FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78622 91177308-0d34-0410-b5e6-96231b3b80d8
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