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* Resolve DanglingDbgValue of PHI nodes where the use follows dbg.value ↵Devang Patel2011-01-241-0/+103
| | | | | | intrinisic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124138 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!Chris Lattner2011-01-241-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124102 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass sret arguments through the stack instead of through registers in Sparc ↵Venkatraman Govindaraju2011-01-221-0/+36
| | | | | | backend. It makes the code generated more compliant with the sparc32 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124030 91177308-0d34-0410-b5e6-96231b3b80d8
* Added ICC, FCC as uses of movcc instruction to generate correct code when ↵Venkatraman Govindaraju2011-01-221-22/+51
| | | | | | -mattr=v9 is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc backend: Venkatraman Govindaraju2011-01-211-16/+34
| | | | | | | | Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-216-39/+65
| | | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for byval arguments in Sparc backend.Venkatraman Govindaraju2011-01-211-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123974 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable support for precise scheduling of the instruction selectionAndrew Trick2011-01-212-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | DAG. Disable using "-disable-sched-cycles". For ARM, this enables a framework for modeling the cpu pipeline and counting stalls. It also activates several heuristics to drive scheduling based on the model. Scheduling is inherently imprecise at this stage, and until spilling is improved it may defeat attempts to schedule. However, this framework provides greater control over tuning codegen. Although the flag is not target-specific, it should have very little affect on the default scheduler used by x86. The only two changes that affect x86 are: - scheduling a high-latency operation bumps the current cycle so independent operations can have their latency covered. i.e. two independent 4 cycle operations can produce results in 4 cycles, not 8 cycles. - Two operations with equal register pressure impact and no latency-based stalls on their uses will be prioritized by depth before height (height is irrelevant if no stalls occur in the schedule below this point). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123971 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-214-17/+17
| | | | | | | | | | | | flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relativeEvan Cheng2011-01-201-2/+6
| | | | | | | | | | value, the "add pc" must be CSE'ed at the same time. We could follow the same approach as T2 by adding pseudo instructions that combine the ldr + "add pc". But the better approach is to use movw + movt (which I will enable soon), so I'll leave this as a TODO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123949 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-201-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123912 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand invalid return values for umulo and smulo. Handle these similarlyEric Christopher2011-01-201-0/+28
| | | | | | | | | | | to add/sub by doing the normal operation and then checking for overflow afterwards. This generally relies on the DAG handling the later invalid operations as well. Fixes the 64-bit part of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123908 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test.Evan Cheng2011-01-201-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123906 91177308-0d34-0410-b5e6-96231b3b80d8
* Sorry, several patches in one.Evan Cheng2011-01-201-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc backend: Implements a delay slot filler that attempt to fill delay slotsVenkatraman Govindaraju2011-01-201-0/+77
| | | | | | | with useful instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123884 91177308-0d34-0410-b5e6-96231b3b80d8
* If we can, lower the multiply part of a umulo/smulo call to a libcallEric Christopher2011-01-201-0/+14
| | | | | | | | | | with an invalid type then split the result and perform the overflow check normally. Fixes the 32-bit parts of rdar://8622122 and rdar://8774702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123864 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix debug info for merged global.Devang Patel2011-01-201-0/+127
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123862 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8878965, a regression I introduced with the recentChris Lattner2011-01-181-0/+32
| | | | | | | llvm.objectsize changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123771 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for mips32 madd and msub instructions. Patch by Akira HatanakaBruno Cardoso Lopes2011-01-181-0/+65
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123760 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an off-by-one error in ctpop combining.Benjamin Kramer2011-01-171-2/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123664 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0.Benjamin Kramer2011-01-171-0/+31
| | | | | | | | | | This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123621 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash SPU BE with memory accesses with big alignmnet.Kalle Raiskila2011-01-171-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123620 91177308-0d34-0410-b5e6-96231b3b80d8
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-173-4/+4
| | | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tests.Rafael Espindola2011-01-166-22/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123591 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR8514, a bug where the "heroic" transformation of shift/and Chris Lattner2011-01-161-0/+36
| | | | | | | | | | into and/shift would cause nodes to move around and a dangling pointer to happen. The code tried to avoid this with a HandleSDNode, but got the details wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123578 91177308-0d34-0410-b5e6-96231b3b80d8
* Spill R4 if it's going to be used to restore SP from FP.Evan Cheng2011-01-161-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123567 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AnalyzeBranch in Sparc Backend.Venkatraman Govindaraju2011-01-161-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123561 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR8981, a crash trying to form a conditional inc with a floating point ↵Chris Lattner2011-01-161-0/+10
| | | | | | compare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123560 91177308-0d34-0410-b5e6-96231b3b80d8
* reapply my fix for PR8961 with a tweak to properly handleChris Lattner2011-01-161-0/+17
| | | | | | | | multi-instruction sequences like calls. Many thanks to Jakob for finding a testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123559 91177308-0d34-0410-b5e6-96231b3b80d8
* revert my fastisel patch again which apparently still gives theChris Lattner2011-01-141-17/+0
| | | | | | | llvm-gcc-i386-linux-selfhost buildbot heartburn... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123431 91177308-0d34-0410-b5e6-96231b3b80d8
* reapply r123414 now that the botz are calmed down and the fix is already in.Chris Lattner2011-01-141-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123427 91177308-0d34-0410-b5e6-96231b3b80d8
* r123414 broke llvm-gcc bootstrap apparently, revertChris Lattner2011-01-141-17/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123422 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR8961 - a fast isel miscompilation where we'd insert a new instructionChris Lattner2011-01-141-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | after sext's generated for addressing that got folded. Previously we compiled test5 into: _test5: ## @test5 ## BB#0: movq -8(%rsp), %rax ## 8-byte Reload movq (%rdi,%rax), %rdi addq %rdx, %rdi movslq %esi, %rax movq %rax, -8(%rsp) ## 8-byte Spill movq %rdi, %rax ret which is insane and wrong. Now we produce: _test5: ## @test5 ## BB#0: movslq %esi, %rax movq (%rdi,%rax), %rax addq %rdx, %rax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123414 91177308-0d34-0410-b5e6-96231b3b80d8
* Experiment with changing the default 32-bit linux stack alignment toEric Christopher2011-01-135-62/+80
| | | | | | | 16 bytes for PR8969. Update all testcases accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123367 91177308-0d34-0410-b5e6-96231b3b80d8
* Try again enabling LiveDebugVariables.Jakob Stoklund Olesen2011-01-123-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123342 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement RETURNADDR and FRAMEADDR lowering in SPARC backend.Venkatraman Govindaraju2011-01-121-0/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123310 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SPARC backend call instruction so that arguments passed through registersVenkatraman Govindaraju2011-01-121-0/+13
| | | | | | | | are correctly marked as used instead of passing all possible argument registers as used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123301 91177308-0d34-0410-b5e6-96231b3b80d8
* The world is not ready for LiveDebugVariables yet.Jakob Stoklund Olesen2011-01-113-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123290 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable LiveDebugVariables by default.Jakob Stoklund Olesen2011-01-113-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123282 91177308-0d34-0410-b5e6-96231b3b80d8
* SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CCVenkatraman Govindaraju2011-01-111-0/+76
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123281 91177308-0d34-0410-b5e6-96231b3b80d8
* Even if we don't have 7 bytes of stack space we may need to save andEric Christopher2011-01-111-0/+40
| | | | | | | | | restore the stack pointer from the frame pointer on thumbv6. Fixes rdar://8819685 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123196 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 8916 (qv for analysis), at least the immediate problem.Dale Johannesen2011-01-101-0/+15
| | | | | | | | | | | | | There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123191 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.Evan Cheng2011-01-082-2/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123048 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-7/+9
| | | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
* Speculatively revert r123032.Devang Patel2011-01-073-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123039 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower some BUILD_VECTORS using VEXT+shuffle.Bob Wilson2011-01-071-0/+59
| | | | | | Patch by Tim Northover. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123035 91177308-0d34-0410-b5e6-96231b3b80d8
* Appropriately truncate debug info range in dwarf output.Devang Patel2011-01-073-3/+58
| | | | | | | Enable live debug variables pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123032 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r122955. It seems using movups to lower memcpy can cause massive ↵Evan Cheng2011-01-0710-78/+96
| | | | | | regression (even on Nehalem) in edge cases. I also didn't see any real performance benefit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123015 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to unbreak the arm buildbot.Benjamin Kramer2011-01-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122999 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcases for PR8411 (vget_low and vget_high implemented as shuffles).Bob Wilson2011-01-071-1/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122997 91177308-0d34-0410-b5e6-96231b3b80d8
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