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* Fix tail merging to assign the (more) correct BasicBlock when splitting.Andrew Trick2013-06-241-2/+2
| | | | | | | | | | | This makes it possible to write unit tests that are less susceptible to minor code motion, particularly copy placement. block-placement.ll covers this case with -pre-RA-sched=source which will soon be default. One incorrectly named block is already fixed, but without this fix, enabling new coalescing and scheduling would cause more failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184680 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MI-Sched support for x86 macro fusion.Andrew Trick2013-06-231-0/+108
| | | | | | | | This is an awful implementation of the target hook. But we don't have abstractions yet for common machine ops, and I don't see any quick way to make it table-driven. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184664 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace with a shorter test case produced by Doug Gillmore.Reed Kotler2013-06-221-6392/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184645 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Don't lose unreferenced non-trivial by-value parametersDavid Blaikie2013-06-211-1/+1
| | | | | | | | | | | | A FastISel optimization was causing us to emit no information for such parameters & when they go missing we end up emitting a different function type. By avoiding that shortcut we not only get types correct (very important) but also location information (handy) - even if it's only live at the start of a function & may be clobbered later. Reviewed/discussion by Evan Cheng & Dan Gohman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184604 91177308-0d34-0410-b5e6-96231b3b80d8
* Add '-mcpu=' to prevent breaking on ATOM due to different code scheduleMichael Liao2013-06-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184591 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add support for selecting CUDA vs OCL mode based on tripleJustin Holewinski2013-06-215-7/+11
| | | | | | IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184579 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing REQUIRES: asserts in crash.ll.Andrew Trick2013-06-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184576 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16360Michael Liao2013-06-211-0/+16
| | | | | | | | | When (srl (anyextend x), c) is folded into (anyextend (srl x, c)), the high bits are not cleared. Add 'and' to clear off them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184575 91177308-0d34-0410-b5e6-96231b3b80d8
* Update physreg live intervals during remat.Andrew Trick2013-06-211-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184574 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Remove a (false) dependency on the memoryoperand's value as we do not useQuentin Colombet2013-06-202-2/+44
| | | | | | | | | | | it at the moment. This allows to form more paired loads even when stack coloring pass destroys the memoryoperand's value. <rdar://problem/13978317> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184492 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Expand sub for v2i32 and v4i32 for SITom Stellard2013-06-201-6/+31
| | | | | | | | | | | Also add a v2i32 test to the existing v4i32 test. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry<awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184482 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Expand add for v2i32 and v4i32Tom Stellard2013-06-201-6/+31
| | | | | | | | | | | | Also add SI tests to existing file and a v2i32 test for both R600 and SI. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184481 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand v2i32 load/store instead of custom loweringTom Stellard2013-06-201-0/+6
| | | | | | | | | | | | | | The custom lowering causes llc to crash with a segfault. Ideally, the custom lowering can be fixed, but this allows programs which load/store v2i32 to work without crashing. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry<awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184480 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: don't use location lists when the location covers the whole ↵David Blaikie2013-06-201-12/+6
| | | | | | | | | | | | | function anyway Fix up three tests - one that was relying on abbreviation number, another relying on a location list in this case (& testing raw asm, changed that to use dwarfdump on the debug_info now that that's where the location is), and another which was added in r184368 - exposing a bug in that fix that is exposed when we emit the location inline rather than through a location list. Fix that bug while I'm here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184387 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: remove accidental test output file.Tim Northover2013-06-181-208/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184236 91177308-0d34-0410-b5e6-96231b3b80d8
* During SelectionDAG building explicitly set a node to constant zero when theQuentin Colombet2013-06-184-5/+41
| | | | | | | | | | | | | value is zero. This allows optmizations to kick in more easily. Fix some test cases so that they remain meaningful (i.e., not completely dead coded) when optimizations apply. <rdar://problem/14096009> superfluous multiply by high part of zero-extended value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184222 91177308-0d34-0410-b5e6-96231b3b80d8
* Reenable, improve, and add MI-Sched unit tests.Andrew Trick2013-06-173-15/+60
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184134 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: PV stores Reg id, not indexVincent Lejeune2013-06-171-0/+50
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184117 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.Vincent Lejeune2013-06-171-0/+44
| | | | | | | Fixes rv7x0 bug in Heaven reported here: https://bugs.freedesktop.org/show_bug.cgi?id=64257 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.Benjamin Kramer2013-06-174-87/+11
| | | | | | | | | | | | | | | | | | The main advantages here are way better heuristics, taking into account not just loop depth but also __builtin_expect and other static heuristics and will eventually learn how to use profile info. Most of the work in this patch is pushing the MachineBlockFrequencyInfo analysis into the right places. This is good for a 5% speedup on zlib's deflate (x86_64), there were some very unfortunate spilling decisions in its hottest loop in longest_match(). Other benchmarks I tried were mostly neutral. This changes register allocation in subtle ways, update the tests for it. 2012-02-20-MachineCPBug.ll was deleted as it's very fragile and the instruction it looked for was gone already (but the FileCheck pattern picked up unrelated stuff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184105 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-162-2/+2
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184066 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: follow up to 184045 to constrain the tests further to ensure they ↵David Blaikie2013-06-154-5/+5
| | | | | | don't contain +0 offsets git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184046 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: print DBG_VALUE MachineInstrs with [] for deref and drop the ↵David Blaikie2013-06-155-6/+6
| | | | | | offset when it's zero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184045 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-153-12/+14
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: Don't print the display name and colon prefix for DEBUG_VALUE ↵David Blaikie2013-06-151-1/+1
| | | | | | comments if the display name is empty git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184026 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add SI load support for v[24]i32 and store for v2i32Tom Stellard2013-06-151-0/+19
| | | | | | | | | | | | Also add a seperate vector lit test file, since r600 doesn't seem to handle v2i32 load/store yet, but we can test both for SI. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184021 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-141-0/+25
| | | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard2013-06-141-0/+3
| | | | | | | | | | We were using RAT_INST_STORE_RAW, which seemed to work, but the docs say this instruction doesn't exist for Cayman, so it's probably safer to use a documented instruction instead. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184015 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark rematerialized super/sub registers as dead.Tim Northover2013-06-141-0/+23
| | | | | | | | | | | | | When we're rematerializing into a not-quite-right register we already add the real definition as an imp-def, but we should also be marking the "official" register as dead, since nothing else is going to use it as a result of this remat. Not doing this can affect pressure tracking. rdar://problem/14158833 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184002 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Fix incorrect condition checks in some cases of folding ↵Stephen Lin2013-06-141-4/+73
| | | | | | FADD/FMUL combinations; also improve accuracy of comments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183993 91177308-0d34-0410-b5e6-96231b3b80d8
* Make PrologEpilogInserter save/restore all callee saved registersDerek Schuff2013-06-142-0/+54
| | | | | | | | | | | in functions which call __builtin_unwind_init() __builtin_unwind_init() is an undocumented gcc intrinsic which has this effect, and is used in libgcc_eh. Goes part of the way toward fixing PR8541. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183984 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX ↵Benjamin Kramer2013-06-141-0/+8
| | | | | | | | equivalent. Give it the right register format so we can also emit it when AVX is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183971 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable FastISel on ARM for Linux and NaCl, not MCJITJF Bastien2013-06-1425-12/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183966 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.Bill Schmidt2013-06-1310-34/+31
| | | | | | | | | | | | | | | | | | | | | | | | | This is a preliminary patch for fast instruction selection on PowerPC. Code generation can differ between DAG isel and fast isel. Existing tests that specify -O0 were written to expect DAG isel. Make this explicit by adding -fast-isel=false to the tests. In some cases specifying -fast-isel=false produces different code even when there isn't a fast instruction selector specified. This is because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel object exists. Thus disabling fast isel can actually produce less conservative code. Because of this, some of the expected code generation in the -O0 tests needs to be adjusted. In particular, handling of function arguments is less conservative with -fast-isel=false (see isOnlyUsedInEntryBlock() in SelectionDAGBuilder.cpp). This results in fewer stack accesses and, in some cases, reduced stack size as uselessly loaded values are no longer stored back to spill locations in the stack. No functional change with this patch; test case adjustments only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183939 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add an IR transformation pass that optimizes calls to sqrt.Akira Hatanaka2013-06-111-0/+32
| | | | | | | | | | The pass emits a call to sqrt that has attribute "read-none". This call will be converted to an ISD::FSQRT node during DAG construction, which will turn into a mips native sqrt instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183802 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-103-6/+8
| | | | | | | | | | | | Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Remove old CONST_NOT_GEN address space that is not being used ↵Justin Holewinski2013-06-101-0/+10
| | | | | | anymore and causes constants to be emitted in the global address space git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183652 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for ARM FastISel load/store register classesJF Bastien2013-06-101-0/+70
| | | | | | r183624 fixed an issue that was tested indirectly. Test it directly with this new test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183634 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-091-0/+6406
| | | | | | | | | | | the Mips16 port. A few of the psuedos could either take signed or unsigned arguments and I did not distinguish the case and improperly rejected some valid cases that the assembler had previously accepted when they were pure pseudos that expanded as assembly instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183633 91177308-0d34-0410-b5e6-96231b3b80d8
* Refine the ARM EHABI test cases.Logan Chien2013-06-099-413/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have ARM unwind directive parser and assembler, we can check the correctness in two stages: 1. From LLVM assembly (.ll) to ARM assembly (.s) 2. From ARM assembly (.s) to ELF object file (.o) We already have several "*.s to *.o" test cases. This CL adds some "*.ll to *.s" test cases and removes the redundant "*.ll to *.o" test cases. New test cases to check "*.ll to *.s" code generator: - ehabi.ll: Check the correctness of the generated unwind directives. - section-name.ll: Check the section name of functions. Removed test cases: - ehabi-mc-cantunwind.ll (Covered by ehabi-cantunwind.ll, and eh-directive-cantunwind.s) - ehabi-mc-compact-pr0.ll (Covered by ehabi.ll, eh-compact-pr0.s, eh-directive-save.s, and eh-directive-setfp.s) - ehabi-mc-compact-pr1.ll (Covered by ehabi.ll, eh-compact-pr1.s, eh-directive-save.s, and eh-directive-setfp.s) - ehabi-mc.ll (Covered by ehabi.ll, and eh-directive-integrated-test.s) - ehabi-mc-section-group.ll (Covered by section-name.ll, and eh-directive-section-comdat.s) - ehabi-mc-section.ll (Covered by section-name.ll, and eh-directive-section.s) - ehabi-mc-sh_link.ll (Covered by eh-directive-text-section.s, and eh-directive-section.s) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183628 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to ARM unwind opcode assembler: * Fix multiple .save or .vsave directives. Besides, the order is preserved now. * For the directives which will generate multiple opcodes, such as ".save {r0-r11}", the order of the unwind opcode is fixed now, i.e. the registers with less encoding value are popped first. * Fix the $sp offset calculation. Now, we can use the .setfp, .pad, .save, and .vsave directives at any order. Changes to test cases: * Add test cases to check the order of multiple opcodes for the .save directive. * Fix the incorrect $sp offset in the test case. The stack pointer offset specified in the test case was incorrect. (Changed test cases: ehabi-mc-section.ll and ehabi-mc.ll) * The opcode to restore $sp are slightly reordered. The behavior are not changed, and the new output is same as the output of GNU as. (Changed test cases: eh-directive-pad.s and eh-directive-setfp.s) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-092-3/+3
| | | | | | the scalar stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc ↵Venkatraman Govindaraju2013-06-081-0/+47
| | | | | | backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183613 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r183552. This time, use a standard type for the option to avoid templateQuentin Colombet2013-06-082-0/+48
| | | | | | | | | | | | | | | | instantiation issue with non-standard type. Add a backend option to warn on a given stack size limit. Option: -mllvm -warn-stack-size=<limit> Output (if limit is exceeded): warning: Stack size limit exceeded (<actual size>) in <functionName>. The longer term plan is to hook that to a clang warning. PR:4072 <rdar://problem/13987214>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183595 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183592 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183587 91177308-0d34-0410-b5e6-96231b3b80d8
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-071-0/+93
| | | | | | | | On PPC32, [su]div,rem on i64 types are transformed into runtime library function calls. As a result, they are not allowed in counter-based loops (the counter-loops verification pass caught this error; this change fixes PR16169). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183581 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert commits related to stack warning.Quentin Colombet2013-06-072-48/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183579 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicit triple in warn stack size test cases to not depend on OS.Quentin Colombet2013-06-072-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183574 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-0/+33
| | | | | | | | | | We weren't computing structure size correctly and we were relying on the original alloca instruction to compute the offset, which isn't always reliable. Reviewed-by: Vincent Lejeune <vljn@ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
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