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* Rename fp-op fusion option (yet again) for compatibility with GCC option.Lang Hames2012-06-224-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159042 91177308-0d34-0410-b5e6-96231b3b80d8
* EmitZerofill should take a 64-bit size or else it's chopping off large ↵Evan Cheng2012-06-221-0/+11
| | | | | | zero-filled global. rdar://11729134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159023 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/Generic/asm-large-immediate.ll: Mark it as XFAIL: powerpc, ↵NAKAMURA Takumi2012-06-221-1/+3
| | | | | | possibly due to r158939. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158994 91177308-0d34-0410-b5e6-96231b3b80d8
* Functions calling __builtin_eh_return must have a frame pointer.Jakob Stoklund Olesen2012-06-221-3/+24
| | | | | | | | | | | | | | The code in X86TargetLowering::LowerEH_RETURN() assumes that a frame pointer exists, but the frame pointer was forced by the presence of llvm.eh.unwind.init which isn't guaranteed. If llvm.eh.unwind.init is actually required in functions calling eh.return (is it?), we should diagnose that instead of emitting bad machine code. This should fix the dragonegg-x86_64-linux-gcc-4.6-test bot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158961 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduling fix: compute predicated implicit use properly.Andrew Trick2012-06-221-3/+3
| | | | | | | | Minor drive by fix to cleanup latency computation. Calling getOperandLatency with a deliberately incorrect operand index does not give you the latency you want. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158959 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from aLang Hames2012-06-224-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | boolean flag to an enum: { Fast, Standard, Strict } (default = Standard). This option controls the creation by optimizations of fused FP ops that store intermediate results in higher precision than IEEE allows (E.g. FMAs). The behavior of this option is intended to match the behaviour specified by a soon-to-be-introduced frontend flag: '-ffuse-fp-ops'. Fast mode - allows formation of fused FP ops whenever they're profitable. Standard mode - allow fusion only for 'blessed' FP ops. At present the only blessed op is the fmuladd intrinsic. In the future more blessed ops may be added. Strict mode - allow fusion only if/when it can be proven that the excess precision won't effect the result. Note: This option only controls formation of fused ops by the optimizers. Fused operations that are explicitly requested (e.g. FMA via the llvm.fma.* intrinsic) will always be honored, regardless of the value of this option. Internally TargetOptions::AllowExcessFPPrecision has been replaced by TargetOptions::AllowFPOpFusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158956 91177308-0d34-0410-b5e6-96231b3b80d8
* The inline asm operand modifier 'n' is suppose Jack Carter2012-06-212-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Negate the immediate constant Several Architectures such as x86 have local implementations of operand modifier 'n' which go beyond the above description slightly. This won't affect them. Affected files: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'n' to the switch cases. test/CodeGen/Generic/asm-large-immediate.ll Generic compiled test (x86 for me) test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158939 91177308-0d34-0410-b5e6-96231b3b80d8
* 1. fix null program output after some other changesAkira Hatanaka2012-06-211-4/+0
| | | | | | | | | | 2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
* Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc ↵Hal Finkel2012-06-211-0/+22
| | | | | | | | stores on PPC. Thanks to Tobias von Koch for pointing out this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158932 91177308-0d34-0410-b5e6-96231b3b80d8
* The inline asm operand modifier 'c' is suppose Jack Carter2012-06-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to be generic across architectures. It has the following description in the gnu sources: Substitute immediate value without immediate syntax Several Architectures such as x86 have local implementations of operand modifier 'c' which go beyond the above description slightly. To make use of the generic modifiers without overriding local implementation one can make a call to the base class method for AsmPrinter::PrintAsmOperand() in the locally derived method's "default" case in the switch statement. That way if it is already defined locally the generic version will never get called. This change is needed when test/CodeGen/generic/asm-large-immediate.ll failed on a native Mips board. The test was assuming a generic implementation was in place. Affected files: lib/Target/Mips/MipsAsmPrinter.cpp: Changed the default case to call the base method. lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Added 'c' to the switch cases. test/CodeGen/Mips/asm-large-immediate.ll Mips compiled version of the generic one Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158925 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r158209, "test/CodeGen/Generic/APIntLoadStore.ll: Mark as XFAIL:ppc ↵NAKAMURA Takumi2012-06-211-1/+0
| | | | | | | | since r157911." It passes according to ppc changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158917 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing llvm.fma -> VFNMS pattern to the ARM backend.Lang Hames2012-06-211-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158902 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit a single _udivmodsi4 libcall instead of two separate _udivsi3 andEvan Cheng2012-06-211-1/+15
| | | | | | | | | _umodsi3 libcalls if they have the same arguments. This optimization was apparently broken if one of the node was replaced in place. rdar://11714607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158900 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the -live-regunits command line option.Jakob Stoklund Olesen2012-06-201-1/+0
| | | | | | Register allocators depend on it being permanently enabled now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158873 91177308-0d34-0410-b5e6-96231b3b80d8
* Only update regunit live ranges that have been precomputed.Jakob Stoklund Olesen2012-06-201-0/+1
| | | | | | | | | | | Regunit live ranges are computed on demand, so when mi-sched calls handleMove, some regunits may not have live ranges yet. That makes updating them easier: Just skip the non-existing ranges. They will be computed correctly from the rescheduled machine code when they are needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158831 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel2012-06-201-0/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't insert 128-bit UNDEF into 256-bit vectors. Just keep the 256-bit ↵Craig Topper2012-06-202-1/+9
| | | | | | vector. Original patch by Elena Demikhovsky. Tweaked by me to allow possibility of covering more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DAG-combines for aggressive FMA formation.Lang Hames2012-06-194-4/+4
| | | | | | | | | | | | | | | | | | | | | | This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple.Jakob Stoklund Olesen2012-06-191-1/+1
| | | | | | The test was failing on Linux because of asm syntax differences. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158748 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen2012-06-191-0/+17
| | | | | | | | | | | | | The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-0/+47
| | | | | | PPC will now generate STWUX and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
* really add a triple :-(Rafael Espindola2012-06-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158696 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple to the test.Rafael Espindola2012-06-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158695 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the support for using .init_array from ARM to the genericRafael Espindola2012-06-191-0/+27
| | | | | | | | | | TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: use NOEN loads and stores if possible when handling struct byval.Manman Ren2012-06-181-0/+14
| | | | | | | | | This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158684 91177308-0d34-0410-b5e6-96231b3b80d8
* This change handles a another case for generating the bic instruction Joel Jones2012-06-181-0/+19
| | | | | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't need to be handled, as the 8 bit constants are encoded directly, thereby not needing a separate load instruction to form the constant into a register. <rdar://problem/11481151> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158659 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a regression test for the bug exposed by r158087, which has beenChandler Carruth2012-06-181-0/+63
| | | | | | | | | | | | | | | | | | | | temporarily reverted. This test is annoyingly overspecified, but I don't know of another way to thoroughly test the saving and restoring of the registers. While this will have to be adjusted even with the issue fixed in order to re-apply r158087, those adjustments should very clearly indicate that it is still correct (%esp getting restored prior to pops), whereas without it, this case can easily slip under the radar. Still, any suggestions for improvements are very welcome. All credit to Matt Beaumont-Gay for reducing this out of an insane Address Sanitizer crash to a reasonably small seg-faulting C program when built with -mstackrealign. I just reduced it to IR, which was much simpler. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158656 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r158087.Chandler Carruth2012-06-183-170/+2
| | | | | | | | | | | | | This patch causes problems when both dynamic stack realignment and dynamic allocas combine in the same function. With this patch, we no longer build the epilog correctly, and silently restore registers from the wrong position in the stack. Thanks to Matt for tracking this down, and getting at least an initial test case to Chad. I'm going to try to check a variation of that test case in so we can easily track the fixes required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158654 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup trip-count finding for PPC CTR loops (and some bug fixes).Hal Finkel2012-06-162-0/+290
| | | | | | | | | | | | | | This cleans up the method used to find trip counts in order to form CTR loops on PPC. This refactoring allows the pass to find loops which have a constant trip count but also happen to end with a comparison to zero. This also adds explicit FIXMEs to mark two different classes of loops that are currently ignored. In addition, we now search through all potential induction operations instead of just the first. Also, we check the predicate code on the conditional branch and abort the transformation if the code is not EQ or NE, and we then make sure that the branch to be transformed matches the condition register defined by the comparison (multiple possible comparisons will be considered). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158607 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: optimization for sub+abs.Manman Ren2012-06-152-3/+21
| | | | | | | | | | | | | | | | This patch will optimize abs(x-y) FROM sub, movs, rsbmi TO subs, rsbmi For abs, we will use cmp instead of movs. This is necessary because we already have an existing peephole pass which optimizes away cmp following sub. rdar: 11633193 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158551 91177308-0d34-0410-b5e6-96231b3b80d8
* Preserve <undef> flags in ARMExpandPseudo.Jakob Stoklund Olesen2012-06-151-0/+8
| | | | | | This probably mostly shows up in bugpoint-generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158527 91177308-0d34-0410-b5e6-96231b3b80d8
* 1. introduce MipsPat in place of Pat in order to exclude those fromAkira Hatanaka2012-06-141-0/+4
| | | | | | | | | | | being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158470 91177308-0d34-0410-b5e6-96231b3b80d8
* Make machine verifier check the first instruction of the last bundle instead ofAkira Hatanaka2012-06-141-0/+21
| | | | | | | | the last instruction of a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158468 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert: test/CodeGen/ARM/iabs.ll in r158441Manman Ren2012-06-141-19/+1
| | | | | | | Sorry that I accidently checked in this file with my previous commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158442 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).Manman Ren2012-06-141-1/+19
| | | | | | | uno && ueq was converted to ueq, it should be converted to uno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158441 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for MIPS long branch pass.Akira Hatanaka2012-06-141-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158438 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test cases.Akira Hatanaka2012-06-145-67/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158435 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement a DAGCombine in MipsISelLowering.cpp which transforms the followingAkira Hatanaka2012-06-131-13/+12
| | | | | | | | | | | pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8
* Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.Akira Hatanaka2012-06-131-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158414 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement fastcc calling convention for MIPS.Akira Hatanaka2012-06-131-0/+253
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158410 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pattern for MKMSK instruction.Richard Osborne2012-06-131-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158409 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix intrinsics for XOP frczss/sd instructions. These instructions only take ↵Craig Topper2012-06-131-12/+12
| | | | | | one source register and zero the upper bits of the destination rather than preserving them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158396 91177308-0d34-0410-b5e6-96231b3b80d8
* disable use of directive .set nomicromipsAkira Hatanaka2012-06-131-1/+1
| | | | | | | | | until this directive is pushed in gas to open source fsf Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158381 91177308-0d34-0410-b5e6-96231b3b80d8
* sched: fix latency of memory dependence chain edges for consistency.Andrew Trick2012-06-131-0/+41
| | | | | | | | | | | For store->load dependencies that may alias, we should always use TrueMemOrderLatency, which may eventually become a subtarget hook. In effect, we should guarantee at least TrueMemOrderLatency on at least one DAG path from a store to a may-alias load. This should fix the standard mode as well as -enable-aa-sched-mi". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm-fast-isel] Add support for -arm-long-calls.Chad Rosier2012-06-122-0/+64
| | | | | | | Patch by Jush Lu <jush.msn@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158368 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test that depends on register allocation.Jakob Stoklund Olesen2012-06-111-5/+4
| | | | | | | The test is really checking the prolog/epilog load/store multiple formation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158328 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test case to work on ARM.Jakob Stoklund Olesen2012-06-111-2/+3
| | | | | | Patch by James Benton! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158316 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-enable the CMN instruction.Bill Wendling2012-06-111-0/+22
| | | | | | | | | | We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable ILP scheduling for all nodes by default on PPC.Hal Finkel2012-06-103-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Over the entire test-suite, this has an insignificantly negative average performance impact, but reduces some of the worst slowdowns from the anti-dep. change (r158294). Largest speedups: SingleSource/Benchmarks/Stanford/Quicksort - 28% SingleSource/Benchmarks/Stanford/Towers - 24% SingleSource/Benchmarks/Shootout-C++/matrix - 23% MultiSource/Benchmarks/SciMark2-C/scimark2 - 19% MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15% (matrix and automotive-bitcount were both in the top-5 slowdown list from the anti-dep. change) Largest slowdowns: MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28% MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26% MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21% SingleSource/Benchmarks/CoyoteBench/lpbench - 20% MultiSource/Applications/d/make_dparser - 16% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158296 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve ext/trunc patterns on PPC64.Hal Finkel2012-06-091-0/+1
| | | | | | | | | | The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that would leave self-moves in the final assembly. Replacing those patterns with ones based on the SUBREG builtins yields better-looking code. Thanks to Jakob and Owen for their suggestions in this matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8
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