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* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-111-0/+188
* Tests: Do not unnecessarily depend on kill commentsMatthias Braun2013-10-101-9/+4
* Tests: Use CHECK-LABEL where possibleMatthias Braun2013-10-104-15/+15
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-101-0/+12
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-1084-86/+86
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-101-0/+1228
* Revert "Implement AArch64 vector load/store multiple N-element structure clas...Rafael Espindola2013-10-101-1228/+0
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-101-0/+1228
* Disable function padding to get this test to pass on atom.Benjamin Kramer2013-10-101-1/+1
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-101-0/+40
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-091-3/+6
* [Sparc] Disable tail call optimization for sparc64.Venkatraman Govindaraju2013-10-091-0/+40
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-091-14/+60
* AArch64: enable MISched by default.Tim Northover2013-10-0911-93/+97
* AArch64: migrate ADRP relaxation test to be llvm-mc only.Tim Northover2013-10-091-27/+0
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. Thi...Craig Topper2013-10-092-3/+7
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-081-0/+69
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-081-0/+49
* Add fabsf to the list of inlined functions; otherwiseReed Kotler2013-10-081-0/+12
* Add some xfaild R600 tests.Matt Arsenault2013-10-083-0/+47
* Let rotr and bswap be handled by expansion for Mips16 since we don'tReed Kotler2013-10-082-0/+8
* Fix a typo in the mattr part of the run line.Craig Topper2013-10-081-1/+1
* Explicitly disable AVX on a bunch of tests so they won't fail on AVX machines...Craig Topper2013-10-086-12/+12
* Remove some instructions that existed to provide aliases to the assembler. Ca...Craig Topper2013-10-084-6/+6
* [mips] Test case for r192124.Akira Hatanaka2013-10-071-0/+33
* Add Mips16 patterns for sign extend byte and sign extend halfword.Reed Kotler2013-10-071-0/+1
* Struct byval: use the correct alignment for loads generated to loadManman Ren2013-10-071-0/+27
* X86: Fix type check. Just because an integer type is illegal doesn't mean it'...Benjamin Kramer2013-10-071-0/+18
* Change objectsize intrinsic to accept different address spaces.Matt Arsenault2013-10-075-13/+13
* [ARM] Improve build attributes emission.Amara Emerson2013-10-072-4/+117
* [AArch64] Add support for NEON scalar arithmetic instructions:Chad Rosier2013-10-072-0/+117
* Add support for aliases with linkonce_odr.Rafael Espindola2013-10-061-0/+3
* Force a CPU that doesn't have AVX, otherwise this test fails.Benjamin Kramer2013-10-061-3/+3
* X86: Don't fold spills into SSE operations if the stack is unaligned.Benjamin Kramer2013-10-061-0/+49
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-062-0/+89
* [Sparc] Do not emit nop after fcmp* instruction with V9.Venkatraman Govindaraju2013-10-062-0/+5
* AVX-512: fixed shuffle loweringElena Demikhovsky2013-10-061-0/+16
* [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.Venkatraman Govindaraju2013-10-061-0/+11
* [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.Venkatraman Govindaraju2013-10-061-0/+39
* Emit a better error when running out of registers on inline asm.Benjamin Kramer2013-10-051-1/+1
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are...Craig Topper2013-10-051-379/+0
* Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (...Craig Topper2013-10-051-0/+20
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-051-0/+476
* Convert test to FileCheck.Rafael Espindola2013-10-051-5/+12
* [Sparc] Use correct alignment while loading/storing fp128 values.Venkatraman Govindaraju2013-10-051-0/+21
* [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with...Venkatraman Govindaraju2013-10-051-0/+13
* [Sparc] Correct the floating point conditional code mapping in GetOppositeBra...Venkatraman Govindaraju2013-10-041-0/+32
* Support tblockaddr for static compilation in Mips16.Reed Kotler2013-10-041-0/+10
* [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasingAkira Hatanaka2013-10-041-2/+6
* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-0/+23
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